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publication number s29cd016_00 revision a amendment 4 issue date november 5, 2004 the contents of this document are subject to change without notice. this document may contain information on a spansion product under development by spansion llc. spansion llc reserves the right to change or discontinue work on any product without notice. the information in this document is provid ed ? as is ? without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third- party rights, or any other warranty, express, implied, or statutory. spansion llc assumes no liability for any damages of any kind arising out of the use of the information in this doc ument. s29cd016g 16 megabit (512 k x 32-bit) cmos 2.5 volt-only burst mode, dual boot, simultaneous read/write flash memory data sheet distinctive characteristics architecture advantages ? simultaneous read/write operations ? two bank architecture: large bank/ small bank ? data can be read from bank while executing erase/ program functions in other bank ? zero latency between read and write operations ? user-defined x32 data bus ? dual boot block ? top and bottom boot sectors in the same device ? flexible sector architecture ? eight 8 kbytes, thirty 64 kbytes, and eight 8 kbytes sectors ? manufactured on 170 nm process technology ? secsi (secured silicon) sector (256 bytes) ? factory locked and identifiabl e: 16 bytes for secure, random factory electronic serial number; remainder may be customer data programmed by spansion? ? customer lockable: can be read, programmed, or erased just like other sectors. once locked, data cannot be changed ? programmable burst interface ? interface to any high performance processor ? modes of burst read operation: ? linear burst : 4 double words and 8 double words with wrap around ? program operation ? ability to perform synchronous and asynchronous write operations of burst configuration register settings independently ? single power supply operation ? optimized for 2.5 to 2.75 volt read, erase, and program operations ? compatibility with jedec standards (jc42.4) ? software compatible with single-power supply flash ? backward-compatible with amd am29lv and am29f and fujitsu mbm29lv and mbm29f flash memories performance characteristics ? high performance read access ? initial/random access times as fast as 54 ns ? burst access time as fast as 9 ns for ball grid array package ? ultra low power consumption ? burst mode read: 90 ma @ 66 mhz max, ? program/erase: 50 ma max ? standby mode: cmos: 60 a max ? 1 million write cycles per sector typical ? 20 year data retention typical ? versatilei/o? control ? device generates data output voltages and tolerates data input voltages as determined by the voltage on the v io pin ? 1.65 v to 2.75 v compatible i/o signals ? 3.6 v tolerant i/o signals software features ? persistent sector protection ? a command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector (requires only v cc levels) ? password sector protection ? a sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-definable 64-bit password ? supports common flash interface (cfi) ? unlock bypass program command ? reduces overall programming time when issuing multiple program command sequences ? data# polling and toggle bits ? provides a software method of detecting program or erase operation completion hardware features ? program suspend/resume & erase suspend/ resume ? suspends program or erase operations to allow reading, programming, or erasing in same bank ? hardware reset (reset#), ready/busy# (ry/ by#), and write protect (wp#) inputs ? acc input ? accelerates programming time for higher throughput during system production ? package options ? 80-pin pqfp ? 80-ball fortified bga
2s29cd016g s29cd016_00_a4 november 5, 2004 advance information general description the s29cd016g is a 16 megabit, 2.5 vo lt-only single power supply burst mode flash memory device. the device can be configured for 524,288 double words. the device can also be programmed in standard eprom programmers. to eliminate bus contention, each device includes separate chip enable (ce#), write enable (we#), and output enable (oe#) controls. additional control inputs are required for synchronous burst operations: load burst address valid (adv#), and clock (clk). each device requires only a single 2.5 or 2.6 volt power supply (2.5 v to 2.75 v) for both read and write functions. a 12.0-volt v pp is not required for program or erase operations, although an acceleration pin is available if faster program- ming performance is required. the device is entirely command set compatible with the jedec single-power- supply flash standard . the software command set is compatible with the com- mand sets of the 5 v am29f and 3 v am29lv flash families. commands are written to the command register using standard microprocessor write timing. register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. write cycl es also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading fr om other flash or eprom devices. the unlock bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. the simultaneous read/w rite architecture provides simultaneous operation by dividing the memory space into two banks. the device can begin programming or erasing in one bank, and then simultaneously read from the other bank, with zero latency. this releases the system fr om waiting for the completion of program or erase operations. see ?simultaneous read/write operations overview and re- strictions? on page 14 . the device provides a 256-byte secsi? (secured silicon) sector with an one- time-programmable (otp) mechanism. in addition, the device features several le vels of sector protection, which can dis- able both the program and erase operations in certain sectors or sector groups: persistent sector protection is a command sector protection method that re- places the old 12 v controlled protection method; password sector protection is a highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted; wp# hardware pro- tection prevents program or erase in the two outermost 8 kbytes sectors of the larger bank. the device defaults to the persistent se ctor protection mode. the customer must then choose if the standard or password protection method is most desirable. the wp# hardware protection feature is always available, independent of the other protection method chosen. the versatilei/o? (v ccq ) feature allows the output voltage generated on the device to be determined based on the v io level. this feature allows this device to operate in the 1.8 v i/o environment, driving and receiving signals to and from other 1.8 v devices on the same bus. the host system can detect whether a prog ram or erase operation is complete by observing the ry/by# pin, by reading the dq7 (data# polling), or dq6 (toggle)
november 5, 2004 s29cd016_00_a4 s29cd016g 3 advance information status bits . after a program or erase cycle is completed, the device is ready to read array data or accept another command. the sector erase architecture allows memory sectors to be erased and repro- grammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc detector that automat- ically inhibits write operations during power transitions. the password and software sector protection feature disables both program and erase opera- tions in any combination of sectors of memory. this can be achieved in-system at v cc level. the program/erase suspend/erase resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. true background erase can thus be achieved. the hardware reset# pin terminates any operation in progress and resets the internal state machine to reading array data. the device offers two power-saving feat ures. when addresses are stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode . power consumption is greatly reduced in both these modes. spansion flash technology combines years of flash memory manufacturing ex- perience to produce the highest levels of quality, reliability and cost effectiveness. the device electrically erases all bits within a sector simultaneously via fowler-nordheim tunnelling. the data is programmed using hot electron injection.
4s29cd016g s29cd016_00_a4 november 5, 2004 advance information table of contents product selector guide . . . . . . . . . . . . . . . . . . . . . .7 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 block diagram of simultaneous read/write circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 connection diagrams . . . . . . . . . . . . . . . . . . . . . . 10 special package handling instructions . . . . . . . 11 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 12 logic symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ordering information . . . . . . . . . . . . . . . . . . . . . . . 14 device bus operations . . . . . . . . . . . . . . . . . . . . . . 15 table 1. device bus operation . . . . . . . . . . . . . . . . . 15 versatilei/o? (v io ) control .............................................................. 15 requirements for reading array data ........................................... 16 simultaneous read/write operations overview and restrictions .......................................... 16 overview ...................................................................................................................... ...... 16 restrictions .................................................................................................................. ...... 16 table 2. bank assignment for boot bank sector devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 simultaneous read/write operations with zero latency ..... 17 table 3. ordering option 00 . . . . . . . . . . . . . . . . . . . 17 table 4. ordering option 01 . . . . . . . . . . . . . . . . . . . 17 writing commands/command sequences ................................... 17 accelerated program and erase operations ..........................................................18 autoselect functions ......................................................................................................18 automatic sleep mode (asm) ........................................................... 18 standby mode .................................................................................................................. .18 reset#: hardware reset pin ............................................................ 19 output disable mode ........................................................................... 19 autoselect mode ................................................................................... 19 table 5. s29cd016g autoselect codes (high voltage meth - od) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 asynchronous read operation (non-burst) ...............................20 figure 1. asynchronous read operation . . . . . . . . . . 21 synchronous (burst) read operation ............................................. 21 linear burst read operations ........................................................... 21 table 6. 32- bit linear and burst data order . . . . . . . 22 ce# control in linear mode ...................................................................................... 23 adv# control in linear mode .................................................................................. 23 reset# control in linear mode ............................................................................... 23 oe# control in linear mode ..................................................................................... 23 ind/wait# operation in linear mode ................................................................. 23 table 7. valid configuration register bit definition for ind/ wait# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 2. end of burst indicator (ind/wait#) timing for linear 4-double-word burst operation . . . . . . . . . . . 24 burst access timing control ...................................................................................... 24 initial burst access delay control ............................................................................ 24 table 8. burst initial access delay . . . . . . . . . . . . . . 24 figure 3. burst access timing . . . . . . . . . . . . . . . . . 25 burst clk edge data delivery ................................................................................... 25 burst data hold control ............................................................................................. 25 asserting reset# during a burst access .............................................................. 25 configuration register ........................................................................ 25 table 9. configuration register definitions . . . . . . . . . 26 table 10. configuration register after device reset . . 28 initial access delay configuration ..................................................28 sector protection . . . . . . . . . . . . . . . . . . . . . . . . . . 28 sector and sector groups ...........................................................................................28 persistent sector protection .......................................................................................28 password sector protection ........................................................................................28 wp# hardware protection .........................................................................................28 persistent sector protection ............................................................ 29 persistent protection bit (ppb) .................................................................................. 29 persistent protection bit lock (ppb lock) ............................................................. 29 dynamic protection bit (dyb) ................................................................................... 29 table 11. sector protection schemes . . . . . . . . . . . . . 30 persistent sector protection mode locking bit ...........................31 password protection mode .................................................................31 password and password mode locking bit ...................................32 64-bit password ............................................................................................................... 32 write protect (wp#) ..........................................................................33 secsi? (secured silicon) sector protection ..................................33 secsi sector protection bit ................................................................34 persistent protection bit lock ..........................................................34 hardware data protection ................................................................34 low v cc write inhibit .................................................................................................. 34 write pulse ?glitch? protection ................................................................................ 34 logical inhibit ............................................................................................................... .... 35 power-up write inhibit ................................................................................................ 35 v cc and v io power-up and power-down sequencing ...................................... 35 table 12. sector addresses for ordering option 00 . . . 35 table 13. sector addresses for ordering option 01 . . . 37 common flash memory interface (cfi) . . . . . . . 39 table 14. cfi query identification string . . . . . . . . . . 39 table 15. cfi system interface string . . . . . . . . . . . . 40 table 16. device geometry definition . . . . . . . . . . . . 41 table 17. cfi primary vendor-specific extended query 42 command definitions . . . . . . . . . . . . . . . . . . . . . . 44 reading array data in non-burst mode ...................................... 44 reading array data in burst mode ................................................ 44 read/reset command .........................................................................45 autoselect command ..........................................................................45 program command sequence ...........................................................45 accelerated program command ..................................................... 46 unlock bypass command sequence .............................................. 46 figure 4. program operation . . . . . . . . . . . . . . . . . . 47 unlock bypass entry command ................................................................................. 47 unlock bypass program command ..........................................................................48 unlock bypass chip erase command ......................................................................48 unlock bypass cfi command ....................................................................................48 unlock bypass reset command ................................................................................48 chip erase command ......................................................................... 48 sector erase command ..................................................................... 49 figure 5. erase operation . . . . . . . . . . . . . . . . . . . . 50 sector erase and program suspend command .......................... 50 sector erase and program suspend operation mechanics .......51 table 18. allowed operations during erase/program sus - pend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 sector erase and program resume command ............................52 configuration register read command ........................................52 configuration register write command ......................................52 common flash interface (cfi) command ....................................52 secsi sector entry command ............................................................53
november 5, 2004 s29cd016_00_a4 s29cd016g 5 advance information password program command .......................................................... 54 password verify command ............................................................... 54 password protection mode locking bit program command . 55 persistent sector protection mode locking bit program com - mand ......................................................................................................... 55 secsi sector protection bit program command ........................ 55 ppb lock bit set command .............................................................. 55 dyb write command ........................................................................ 56 password unlock command ............................................................. 56 ppb program command ..................................................................... 56 all ppb erase command .................................................................... 57 dyb write .............................................................................................. 57 ppb lock bit set .................................................................................... 57 dyb status .............................................................................................. 57 ppb status ............................................................................................... 57 ppb lock bit status .............................................................................. 57 non-volatile protection bit program and erase flow ............. 58 table 19. memory array command definitions (x32 mode) 59 table 20. sector protection command definitions (x32 mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 write operation status . . . . . . . . . . . . . . . . . . . . . 61 dq7: data# polling ............................................................................... 61 figure 6. data# polling algorithm . . . . . . . . . . . . . . 62 ry/by#: ready/busy# ......................................................................... 63 dq6: toggle bit i .................................................................................. 63 dq2: toggle bit ii ................................................................................ 64 reading toggle bits dq6/dq2 ........................................................ 64 figure 7. toggle bit algorithm . . . . . . . . . . . . . . . . . 65 dq5: exceeded timing limits .......................................................... 66 dq3: sector erase timer .................................................................. 66 table 21. write operation status . . . . . . . . . . . . . . . 66 absolute maximum ratings . . . . . . . . . . . . . . . . . . 67 figure 8. maximum negative overshoot waveform . . 67 figure 9. maximum positive overshoot waveform . . . 67 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . 67 industrial (i) devices ...................................................................................................... 67 extended (e) devices .................................................................................................... 67 v cc supply voltages ...................................................................................................... 67 v io supply voltages ....................................................................................................... 67 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . .68 table 22. cmos compatible . . . . . . . . . . . . . . . . . . . 68 figure 10. i cc1 current vs. time (showing active and auto - matic sleep currents) . . . . . . . . . . . . . . . . . . . . . . . 69 figure 11. typical i cc1 vs. frequency . . . . . . . . . . . . 69 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 12. test setup . . . . . . . . . . . . . . . . . . . . . . . 70 table 23. test specifications . . . . . . . . . . . . . . . . . . . 70 key to switching waveforms . . . . . . . . . . . . . . . . 70 switching waveforms . . . . . . . . . . . . . . . . . . . . . . 70 figure 13. input waveforms and measurement levels 70 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . .71 figure 14. v cc and v io power-up diagram. . . . . . . . . 71 table 24. asynchronous read operations . . . . . . . . . . 72 figure 15. conventional read operations timings . . . 72 table 25. burst mode read . . . . . . . . . . . . . . . . . . . . 73 figure 16. burst mode read (x32 mode) . . . . . . . . . . 74 figure 17. asynchronous command write timing . . . . 75 figure 18. synchronous command write/read timing 75 table 26. hardware reset (reset#) . . . . . . . . . . . . . 76 figure 19. reset# timings . . . . . . . . . . . . . . . . . . . 76 figure 20. wp# timing . . . . . . . . . . . . . . . . . . . . . . 77 table 27. erase/program operations . . . . . . . . . . . . . 78 figure 21. program operation timings . . . . . . . . . . . 79 figure 22. chip/sector erase operation timings. . . . . 80 figure 23. back-to-back cycle timings . . . . . . . . . . . 80 figure 24. data# polling timings (during embedded algorithms) . . . . . . . . . . . . . . . . 81 figure 25. toggle bit timings (during embedded algorithms) . . . . . . . . . . . . . . . . 81 figure 26. dq2 vs. dq6 for erase/erase suspend operations 82 figure 27. synchronous data polling timing/toggle bit tim - ings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 28. sector protect/unprotect timing diagram . 83 table 28. alternate ce# controlled erase/program opera - tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 29. alternate ce# controlled write operation tim - ings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 29. erase and programming performance . . . . . 86 table 30. pqfp and fortified bga pin capacitance . . . . 86 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . 87 prq080?80-lead plastic quad flat package 87 laa080?80-ball fortified ball grid array (13 x 11 mm) 88 revision summary . . . . . . . . . . . . . . . . . . . . . . . . . 89
6s29cd016g s29cd016_00_a4 november 5, 2004 advance information product selector guide part number s29cd016g standard voltage range: v cc = 2.5 ? 2.75 v synchronous/burst or asynchronous speed option (clock rate) 0p (66 mhz) 0m (56 mhz) 0j (40 mhz) max initial/asynchronous access time, ns (t acc ) 54 64 67 max burst access delay (ns) 9 fbga/ 9.5 pqfp 10 fbga/ 10 pqfp 17 max clock rate (mhz) 66 56 40 min initial clock delay (clock cycles) see figure 3 4 4 3 max ce# access, ns (t ce )586971 max oe# access, ns (t oe )202028
november 5, 2004 s29cd016_00_a4 s29cd016g 7 advance information block diagram input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss we# acc wp# reset# ce# oe# dq0 ? dq31 a0?a18 data latch y-gating cell matrix address latch dq0?dq15 a0?a18 burst state control burst address counter adv# clk a0?a18 v io ind/ wait# ry/by#
8s29cd016g s29cd016_00_a4 november 5, 2004 advance information block diagram of simultaneous read/write circuit v cc v ss upper bank address a0?a18 reset# we# ce# adv# dq0?dq31 state control & command register x-decoder y-decoder latches and control logic oe# dq0?dq31 lower bank (bank 0) y-decoder x-decoder latches and control logic lower bank address status control a0?a18 a0?a18 a0?a18 a0?a18 dq0?dq31 dq0?dq31 ry/by# upper bank (bank 1)
november 5, 2004 s29cd016_00_a4 s29cd016g 9 advance information connection diagram s 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 dq16 dq17 dq18 dq19 v ccq v ss dq20 dq21 dq22 dq23 dq24 dq25 dq26 dq27 v ccq v ss dq28 dq29 dq30 dq31 mch a0 a1 a2 dq15 dq14 dq13 dq12 v ss v ccq dq11 dq10 dq9 dq8 dq7 dq6 dq5 dq4 v ss v ccq dq3 dq2 dq1 dq0 nc a18 a17 a16 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 mch ind/wait# nc wp# we# oe# ce# v cc nc v ss adv# ry/by# nc clk reset# v ccq a3 a4 a5 a6 a7 a8 v ss acc v cc a9 a10 a11 a12 a13 a14 a15 25 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80-pin pqfp to p v i e w
10 s29cd016g s29cd016_00_a4 november 5, 2004 advance information connection diagrams special package handling instructions special handling is required for flash memory products in molded packages (bga). the package and/or data integrity may be compromised if the package body is exposed to temperatures abov e 150c for prolonged periods of time. b3 c3 d3 e3 f3 g3 h3 b4 c4 d4 e4 f4 g4 h4 b5 c5 d5 e5 f5 g5 h5 b6 c6 d6 e6 f6 g6 h6 b7 c7 d7 e7 f7 g7 h7 b8 c8 d8 e8 f8 g8 h8 dq20 v ccq v ss v ccq dq29 a0 a1 dq18 dq23 dq24 dq26 dq30 mch a4 dq19 dq21 dq25 dq28 dq31 a7 a5 dq17 dq22 ry/by# dq27 nc nc a8 wp# dq9 dq5 dq1 nc a10 a9 dq11 dq10 dq6 dq2 nc a11 a12 a3 a4 a5 a6 a7 a8 a2 a3 a6 v ss acc v cc b2 c2 d2 e2 f2 g2 h2 dq12 dq8 dq7 dq4 dq0 a18 a13 a2 a14 b1 c1 d1 e1 f1 g1 h1 dq13 j3 j4 j5 j6 j7 j8 dq16 ind/wait# oe# ce# nc adv# j2 dq14 j1 dq15 k3 k4 k5 k6 k7 k8 mch nc we# v cc v ss clk k2 reset# k1 v ccq v ccq v ss v ccq dq3 a17 a16 a1 a15 80-ball fortified bga (balls facing down)
november 5, 2004 s29cd016_00_a4 s29cd016g 11 advance information pin configuration a0?a18 = 19-bit address bus for 16 mb device. a9 supports 12 v autoselect inputs. dq0?dq31 = 32-bit data inputs/outputs/float ce# = chip enable input. this signal is asynchronous relative to clk for the burst mode. oe# = output enable input. this signal is asynchronous relative to clk for the burst mode. we# = write enable. this signal is asynchronous relative to clk for the burst mode. v ss = device ground nc = pin not connected internally r y / b y # = re a d y / b us y o u t p ut a n d o p e n d ra i n. w h e n r y / b y # = v ih , the device is ready to accept read operations and commands. when ry/by# = v ol , the device is either executing an embedded algorithm or the device is executing a hardware reset operation (a pull-up resistor is required.). clk = clock input that can be tied to the system or microprocessor clock and provides the fundamental timing and internal operating frequency. adv# = load burst address input. indicates that the valid address is present on the address inputs. ind/wait# = end of burst indicator for finite bursts only. ind/ wait# is low when the last word in the burst sequence is at the data outputs. otherwise the ind/ wait# is high when ce# is low. wp# = write protect input. when wp# = v ol , the two outermost bootblock sector in the 75% bank are write protected regardless of other sector protection configurations. acc = acceleration input. when taken to 12 v, program and erase operations are accelerated. when not used for acceleration, acc = v ss or v cc . v io (v ccq ) = output buffer power supply (1.65 v to 2.75 v, 3.6 v tolerant) v cc = chip power supply (2.5 v to 2.75 v) reset# = hardware reset input mch = must connect high (to v cc )
12 s29cd016g s29cd016_00_a4 november 5, 2004 advance information logic symbols x32 mode 19 32 dq0?dq31 a0?a18 clk ry/by# ce# oe# we# reset# adv# acc wp# v io (v ccq ) ind/wait#
november 5, 2004 s29cd016_00_a4 s29cd016g 13 advance information ordering information the order number (valid combination) is formed by the following: valid combinations valid combinations list configurations planned to be supported in volume for this device. consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. s29cd016g 0j f a i 00 0 packing type 0 = tray 2 = 7? tape and reel 3 = 13? tape and reel additional ordering options 00 = 4 mb in bank 0, 12 mb in bank 1, wp# protects sectors 44 and 45 01 = 12 mb in bank 0, 4 mb in bank 1, wp# protects sectors 0 and 1 temperature range i = industrial (?40 c to +85 c) n = extended (?40 c to +125 c) material set a=standard package type q = plastic quad flat package (pqfp) f = ball fortified ball grid array, 1.0 mm pitch package clock frequency 0j = 40 mhz 0m = 56 mhz 0p = 66 mhz device number/description s29cd016g 16 megabit (512k x 32-bit) cmos 2.5 volt-only burst mode, dual boot, simultaneous read/write flash memory manufactured on 170 nm floating gate technology valid combinations for pqfp packages clock frequency s29cd016g0p qai00 qai01 qan00 qan01 66 mhz s29cd016g0m 56 mhz s29cd016g0j 40 mhz valid combinations for fortified bga packages clock frequency order number package marking s29cd016g0p fai00 fai01 fan00 fan01 cd016g0pfa i00 i01 n00 n01 66 mhz s29cd016g0m cd016g0mfa 56 mhz s29cd016g0j cd016g0jfa 40 mhz
14 s29cd016g s29cd016_00_a4 november 5, 2004 advance information device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory location. the register is com- posed of latches that store the commands, along with the address and data information needed to execute the comma nd. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. ta b l e 1 lists the device bus operations, the inputs and con- trol levels they require, and the resulting output. the following subsections describe each of these operations in further detail. legend: l = logic low = v il , h = logic high = v ih , x = don?t care. notes: 1. wp# controls the two outermost sectors of the top boot block or the two outermost sectors of the bottom boot block. 2. dq0 reflects the sector ppb (or sector group ppb) and dq1 reflects the dyb. ve rs at i le i/ o? ( v io ) control the versatilei/o (v io ) control allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data in- puts to the same voltage level that is asserted on the v io pin. ta b l e 1 . d e v i c e b u s o p e r a t i o n operation ce# oe# we# reset# clk adv# addresses data (dq0?dq31) read l l h h x x a in d out asynchronous write l h l h x x a in d in synchronous write l h l h a in d in standby (ce#) h x x h x x x high z output disable l h h h x x high z high z reset x x x l x x x high z ppb protection status (note 2) l l h h x x sector address, a9 = v id , a7 ? a0 = 02h 00000001h, (protected) a6 = h 00000000h (unprotect) a6 = l burst read operations load starting burst address l x h h a in x advance burst to next address with appropriate data presented on the data bus l l h h h x burst data out terminate current burst read cycle hxh h x x high z terminate current burst read cycle with reset# xxh l xx x high z terminate current burst read cycle; start new burst read cycle lhh h a in x
november 5, 2004 s29cd016_00_a4 s29cd016g 15 advance information the output voltage generated on the de vice is determined based on the v io (v ccq ) level. a v io of 1.65?1.95 volts is targeted to provide for i/o tolerance at the 1.8 volt level. a v cc and v io of 2.5?2.75 volts makes the device appear as 2.5 volt-only. requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output control and gates array data to the output pins. we# should remain at v ih . the internal state machine is set for rea ding array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard micr oprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. address access time (t acc ) is the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable addresses and stable ce# to valid data at the output pins. the output enable access time (t oe ) is the delay from the falling edge of oe# to valid data at the output pins (assum- ing the addresses are stable for at least t acc ?t oe time and ce# is asserted for at least t ce ?t oe time). see ? ?reading array data in non-burst mode? on page 42 ? for more information. refer to the ac read operations table for timing specifications and to ta b l e 1 o n page 20 for the timing diagram. i cc1 in the dc characteristics table represents the active current specification for reading array data. simultaneous read/write operations overview and restrictions overview the simultaneous read/write feature allows a program or erase operation to be executed in one (busy) bank, while perfor ming other operations in the other bank (non-busy). the simultaneous read/write operation of this device was optimized for applica- tions that could most benefit from this capability. these applications store code in the larger bank, while storing data in the smaller bank. the best example of this is when a sector erase operation (a s an embedded operation) in the smaller (busy) bank occurs, while performing a burst/synchronous read operation in the larger (non-busy) bank. restrictions the simultaneous read/write function is tested by executing an embedded op- eration in the small (busy) bank while performing other operations in the big (non-busy) bank. however, the opposite case is neither tested nor valid. that is, it is not tested by executing an embedde d operation in the big (busy) bank while performing other operations in the small (non-busy) bank. see the following ta- bles, table 2 on page 16 , table 18 on page 50 , table 12 on page 34 , and table 13 on page 36
16 s29cd016g s29cd016_00_a4 november 5, 2004 advance information ta b l e 2 . bank assignment for boot bank sector devices simultaneous read/write operations with zero latency the device is capable of reading data from one bank of memory while program- ming or erasing in the other bank of memory. an erase operation may also be suspended to read from or program to another location within the same bank (ex- cept the sector being erased). refer to the table in ?dc characteristics? on page 67 for read-while-program and read-while-erase current specifications. simultaneous read/write operations are valid for both the main flash memory array and the secsi otp sector. simultaneo us read/write is disabled during the cfi and password program/verify operations. ppb program/erase operations and the password unlock operation permit rea ding data from th e large (75%) bank while reading the operation status of these commands from the small (25%) bank. ta b l e 3 . ordering option 00 ta b l e 4 . ordering option 01 writing commands/command sequences to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . the device features an unlock bypass mode to facilitate faster programming. once the device enters the unlock bypass mode, only two write cycles are re- quired to program a word or byte, instead of four. the ?sector erase and program suspend command? on page 49 contains details on programming data to the de- vice using both standard and unlock bypass command sequences. an erase operation can erase one sector, multiple sectors, or the entire device. table 12 on page 34 and table 13 on page 36 indicate the address space that each sector occupies. a ?sector address? consists of the address bits required to uniquely select a sector. the ?command definitions? on page 43 contain details regarding erasing a sector or the entire chip, or suspending/resuming the erase operation. after the system writes the autoselect command sequence, the device enters the autoselect mode. the system can then read autoselect codes from the internal register (which is separate from the memory array) on dq7?dq0. standard read bank ordering option 00 ordering option 01 bank 0 small bank big bank bank 1 big bank small bank bank a18:a17 bank 0 00 bank 1 01, 1x bank a18:a17 bank 0 0x, 10 bank 1 11
november 5, 2004 s29cd016_00_a4 s29cd016g 17 advance information cycle timing applies in this mode. refer to ?autoselect mode? on page 18 for more information. i cc2 and i cc3 in the dc characteristics table rep resents the active current speci- fication for erase or program modes. the ?ac characteristics? on page 70 section contains timing specification tables and timing diagrams for erase or program operations. when in synchronous read mode configuration, the device is able to perform both asynchronous and synchronous write operations. clk and adv# address latch is supported in synchronous programming mode. during a synchronous write oper- ation, to write a command or command sequence, (which includes programming data to the device and erasing sectors of memory), the system must drive adv# and ce# to vil, and oe# to vih when providing an address to the device, and drive we# and ce# to vil, and ce# to vih, when writing commands or data. accelerated program and erase operations the device offers accelerated program/erase operations through the acc pin. when the system asserts v hh (12v) on the acc pin, the device automatically en- ters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequence to do accelerated programming. the device uses the higher voltage on the acc pin to accelerate the operation. a sector that is being protected with the wp# pin is st ill protected during accelerated program or erase. note that the acc pin must not be at v hh during any operation other than accelerated programming, or device damage may result. when accelerated program/erase is not in use, set acc=v ss or acc=v cc . autoselect functions if the system writes the autoselect command sequence, the device enters the au- toselect mode. the system can then read autoselect codes from the internal register (which is separate from the memory array) on dq7?dq0. standard read cycle timings apply in this mode. refer to the ?autoselect mode? on page 18 and ?autoselect command? on page 44 sections for more information. automatic sleep mode (asm) the automatic sleep mode minimizes flash device energy consumption. while in asynchronous mode, the device automatically enables this mode when addresses remain stable for t acc + 60 ns. the automatic sleep mode is independent of the ce#, we# and oe# control signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. while in synchronous mode, the de- vice automatically enables this mode when either the first active clk level is greater than t acc or the clk runs slower than 5 mhz. note that a new burst op- eration is required to provide new data. i cc8 in the ?dc characteristics? section represents the automatic sleep mode cur- rent specification. standby mode when the system is not responding or writing to the device, it can place the de- vice in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input.
18 s29cd016g s29cd016_00_a4 november 5, 2004 advance information the device enters the cmos standby mode when the ce# and reset# inputs are both held at vcc 0.2 v. the device requires standard access time (t ce ) for read access, before it is ready to read data. if the device is deselected during erasure or programming, the device draws ac- tive current until the operation is completed. i cc5 in the ?dc characteristics? section represents the standby current specification. caution : entering the standby mode via the reset# pin also resets the device to the read mode and floats the data i/o pins. furthermore, entering i cc7 during a program or erase operation l leaves erroneous data in the address locations being operated on at the time of the reset# pulse. these locations require up- dating after the device resumes standard operations. refer to ??reset#: hardware reset pin? on page 18 for further discussion of the reset# pin and its functions. reset#: hardware reset pin the reset# pin is an active low signal th at is used to reset the device under any circumstances. a logic ?0? on this pin forces the device out of any mode that is currently executing back to the reset state. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the device. to avoid a potential bus contention during a system reset, the device is isolated from the dq data bus by tristating the data output pins for the duration of the reset pulse. all pins are ?don?t care? during the reset operation. if reset# is asserted during a program or erase operation, the ry/by# pin re- mains low until the reset operation is internally complete. this action requires between 1 s and 7s for either chip erase or sector erase. the ry/by# pin can be used to determine when the reset oper ation is complete. otherwise, allow for the maximum reset time of 11 s. if reset# is asserted when a program or erase operation is not executing (ry/by# = ?1?), the reset operation completes within 500 ns. the simultaneous read/write feature of this device allows the user to read a bank after 500 ns if the bank was in the read/reset mode at the time re- set# was asserted. if one of the banks was in the middle of either a program or erase operation when reset# was asserted, the user must wait 11 s before ac- cessing that bank. asserting reset# during a program or erase operation leaves erroneous data stored in the address locations being oper ated on at the time of device reset. these locations need updating after the reset operation is complete. see figure 19, on page 75 for timing specifications. asserting reset# active during v cc and v io power-up is required to guarantee proper device initialization until v cc and v io have reached their steady state voltages. output disable mode see table 1 on page 14 for oe# operation in output disable mode. autoselect mode the autoselect mode provides manufacturer and device identification, and sector protection verification, through identifi er codes output on dq7?dq0. this mode is primarily intended for programming equipment to automatically match a device
november 5, 2004 s29cd016_00_a4 s29cd016g 19 advance information to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id on ad- dress pin a9. address pins a6, a1, and a0 must be as shown in table 12 on page 34 (top boot devices) or table 13 on page 36 (bottom boot devices). in ad- dition, when verifying sector protection, the sector address must appear on the appropriate highest order add ress bits (see tables 1 and). ta b l e 5 shows the re- maining address bits that are don?t care. when all necessary bits are set as required, the programming equipment may then read the corresponding identi- fier code on dq7?dq0. to access the autoselect codes in-system, the host system can issue the autose- lect command via the command. this method does not require v id . see ?command definitions? on page 43 for details on using the autoselect mode. ta b l e 5 . s29cd016g autoselect codes (high voltage method) l = logic low = v il , h = logic high = v ih , sa = sector address, x = don?t care. note: the autoselect codes may also be accessed in-system via command sequences. see tables 18 and 20. asynchronous read operation (non-burst) the device includes two control functions which must be satisfied in order to ob- tain data at the outputs. ce# is the power control and should be used for device selection. oe# is the output control and should be used to gate data to the output pins if the device is selected. the device is power-up in an asynchronous read mode. in the asynchronous mode the device includes two control functions which must be satisfied in order to obtain data at the outputs. ce# is the power control and should be used for device selection. oe# is the output control and should be used to gate data to the output pins if the device is selected. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from the stable ad- dresses and stable ce# to valid data at the output pins. the output enable access time is the delay from the falling edge of oe# to valid data at the output pins (assuming the addresses are stable for at least t acc ?t oe time). description ce# oe# we# a18 to a11 a10 a9 a8 a7 a6 a5 to a4 a3 a2 a1 a0 dq7 to dq0 manufacturer id : spansion ll hxxv id xxlxllll 0001h autoselect device code read cycle 1 l l h x x v id xllxlllh 007eh read cycle 2 l l h x x v id x l l lhhh l 0036h read cycle 3 l l h x x v id x l l lhhhh 0000h ordering option 00 0001h ordering option 01 ppb protection status ll hsaxv id xlllllhl 0000h (unprotected) 0001h (protected)
20 s29cd016g s29cd016_00_a4 november 5, 2004 advance information note: operation is shown for the 32-bit data bus. figure 1. asynchronous read operation synchronous (burst) read operation the device is capable of performing burs t read operations to improve total system data throughput. the 2, 4, and 8 double word accesses are configurable as linear burst accesses. all burst operations provide wrap around linear burst accesses. additional options for all burst modes include initial access delay configurations (2?16 clks) device configuration for burst mode operation is accomplished by writing the configuration register with the desired burst configuration informa- tion. once the configuration register is wr itten to enable burst mode operation, all subsequent reads from the array are returned using the burst mode protocols. like the main memory access, the secsi sector memory is accessed with the same burst or asynchronous timing as defined in the configuration register. how- ever, the user must recognize burst operations past the 256 byte secsi boundary returns invalid data. burst read operations occur only to the main flash memory arrays. the configu- ration register and protection bits are t reated as single cycle reads, even when burst mode is enabled. read operations to these locations results in the data re- maining valid while oe# is at v il , regardless of the number of clk cycles applied to the device. linear burst read operations linear burst read mode reads either 2, 4, or 8 double words (1 double word = 32 bits). (see table 6 on page 21 for all valid burst output sequences). the ind/ wait# pin transitions active (v il ) during the last transfer of data during a linear burst read before a wrap around, indicating that the system should initiate an- other adv# to start the next burst access. if the system continues to clock the device, the next access wraps around to the starting address of the previous burst access. the ind/wait# signal remains inactive (floating) when not active. see table 6 on page 21 for a complete 32-bit data bus interface order. d0 d1 d2 d3 d3 ce# clk adv# addresses data oe# we# i nd/wait# v ih float v oh address 0 address 1 address 2 address 3 flo at
november 5, 2004 s29cd016_00_a4 s29cd016g 21 advance information ta b l e 6 . 32- bit linear and burst data order data transfer sequence (independent of the word# pin) output data sequence (initial access address) two li nea r da ta tra ns fer s 0-1 (a0 = 0) 1-0 (a0 = 1) four linear data transfers 0-1-2-3 (a1-a0 = 00) 1-2-3-0 (a1-a0 = 01) 2-3-0-1 (a1-a0 = 10) 3-0-1-2 (a1-a0 = 11) eight linear data transfers 0-1-2-3-4-5-6-7 (a2-a0 = 000) 1-2-3-4-5-6-7-0 (a2-a0 = 001) 2-3-4-5-6-7-0-1 (a2-a0 = 010) 3-4-5-6-7-0-1-2 (a2-a0 = 011) 4-5-6-7-0-1-2-3 (a2-a0 = 100) 5-6-7-0-1-2-3-4 (a2-a0 = 101) 6-7-0-1-2-3-4-5 (a2-a0 = 110) 7-0-1-2-3-4-5-6 (a2-a0 = 111)
22 s29cd016g s29cd016_00_a4 november 5, 2004 advance information ce# control in linear mode the ce# (chip enable) pin enables the device during read mode operations. ce# must meet the required burst read setup times for burst cycle initiation. if ce# is taken to v ih at any time during the burst linear or burst cycle, the device im- mediately exits the burst sequence and fl oats the dq bus and ind/wait# signal. restarting a burst cycle is accomplished by taking ce# and adv# to v il . adv# control in linear mode the adv# (address valid) pin is used to initiate a linear burst cycle at the clock edge when ce# and adv# are at v il and the device is configured for either linear burst mode operation. a burst access is initiated and the address is latched on the first rising clk edge when adv# is active or upon a rising adv# edge, which- ever occurs first. if the adv# signal is taken to v il prior to the end of a linear burst sequence, the previous address is discarded and subsequent burst transfers are invalid until adv# transitions to v ih before a clock edge, which initiates a new burst sequence. reset# control in linear mode the reset# pin immediately halts the linear burst access when taken to v il . the dq data bus and ind/wait# signal float. additionally, the configuration register contents are reset back to the default condition where the device is placed in asynchronous access mode. oe# control in linear mode the oe# (output enable) pin is used to enable the linear burst data on the dq data bus and the ind/wait# pin. de-asserting the oe# pin to v ih during a burst operation floats the data bus and the ind/wait# pin. however, the device con- tinues to operate internally as if the burst sequence continues until the linear burst is complete. the oe# pin does not halt the burst sequence, this is accom- plished by either taking ce# to v ih or re-issuing a new adv# pulse. the dq bus and ind/wait# signal remain in the float state until oe# is taken to v il . ind/wait# operation in linear mode the ind/wait#, or end of burst indicator signal (when in linear modes), informs the system that the last address of a burst sequence is on the dq data bus. for example, with a 2-double-word linear burst, the ind/wait# signal transitions ac- tive on the second access. if the same scenario is used, the ind/wait# signal has the same delay and setup timing as the dq pins. also, the ind/wait# signal is controlled by the oe# signal. if oe# is at v ih , the ind/wait# signal floats and is not driven. if oe# is at v il , the ind/wait# signal is driven at v ih until it tran- sitions to v il indicating the end of burst sequence. the ind/wait# signal timing and duration is (see ?configuration register? on page 24 for more information). ta b l e 7 lists the valid combinations of the configuration register bits that impact the ind/wait# timing. ta b l e 7 . valid configuration register bit definition for ind/wait# doc wc cc definition 0 0 1 ind/wait# = vil for 1-clk cycle, active on last transfer, driven on rising cld edge 0 1 1 ind/wait# = vil for 1-clk cycle, active on second to last transfer, driven on rising clk edge
november 5, 2004 s29cd016_00_a4 s29cd016g 23 advance information burst access timing control in addition to the ind/wait# signal control, burst controls exist in the control register for initial access delay, delivery of data on the clk edge, and the length of time data is held. initial burst access delay control the device contains options for initial access delay of a burst access. the initial access delay has no effect on asynchronous read operations. burst initial access delay is defined as the number of clock cycles that must elapse from the first valid clock edge aft er adv# assertion (or the rising edge of adv#) until the first valid clk edge when the data is valid. the burst access is initiated and the addres s is latched on the first rising clk edge when adv# is active or upon a rising adv# edge, whichever comes first. ( ta b l e 8 shows the initial access delay configurations.) figure 2. end of burst indicator (ind/wait#) timing for linear 4-double-word burst operation table 8. burst initial access delay (sheet 1 of 2) cr13 cr12 cr11 cr10 initial burst access (clk cycles) 0000 2 0001 3 0010 4 0011 5 ce# clk adv# addresses oe# data address 1 invalid d1 d2 d3 d0 address 1 latched 3 clock delay ind/wait# v il v ih note: operation is shown for the 32-bit data bus. figure shown with 3-clk initial access delay configuration, linear address, 4-double-word burst, output on rising clk edge, data hold for 1-clk, ind / wait# asserted on the last transfer before wrap-around
24 s29cd016g s29cd016_00_a4 november 5, 2004 advance information figure 3. burst access timing notes: 1. burst access starts with a rising clk edge and when adv# is active. 2. configurations register 6 must be always set to 1 (cr6 = 1). burst starts and data outputs on the rising clk edge. 3. cr [13-10] = 0001 or three clock cycles 4. cr [13-10] = 0010 or four clock cycles 5. cr [13-10] = 0011 or five clock cycles burst clk edge data delivery the device is capable of delivering data on either the rising or falling edge of clk. to deliver data on the rising edge of clk, bit 6 in the control register (cr6) is set to 1. the default configuration is set to the rising edge. burst data hold control the device is capable of holding data for one clks. the default configuration is to hold data for one clk and is the only valid state. asserting reset# during a burst access if reset# is asserted low during a burs t access, the burst access is immediately terminated and the device defaults back to asynchronous read mode. refer to ?reset#: hardware reset pin? on page 18 for more information on the reset# function. configuration register the device contains a configuration register for configuring read accesses. the configuration register is accessed by the configuration register read and the configuration register write commands. th e configuration register does not oc- 0100 6 0101 7 0 1 1 0 8 0111 9 table 8. burst initial access delay (sheet 2 of 2) cr13 cr12 cr11 cr10 initial burst access (clk cycles) clk adv# addresses dq31-dq0 3 dq31-dq0 4 dq31-dq0 5 valid address three clk delay 2nd clk 3rd clk 4th clk 5th clk 1st clk four clk delay address 1 latched five clk delay d0 d1 d2 d3 d0 d1 d2 d0 d1 d2 d3 d4
november 5, 2004 s29cd016_00_a4 s29cd016g 25 advance information cupy any addressable memory locati on, but rather, is accessed by the configuration register commands. the co nfiguration register is readable any time, however, writing the configuration register is restricted to times when the embedded algorithm? is not active. if the user attempts to write the configura- tion register while the embedded algorithm? is active, the write operation is ignored and the contents of the co nfiguration register remain unchanged. the configuration register is a 16 bit data field which is accessed by dq15?dq0. during a read operation, dq31?dq16 returns all zeroes. ta b l e 9 shows the con- figuration register. also, configuration register reads operate the same as autoselect command reads. when the command is issued, the bank address is latched along with the command. reads operations to the bank that was specified during the configuration register read command return configuration register contents. read operations to the other bank return flash memory data. either bank address is permitted when writing the configuration register read command. ta b l e 9 . configuration register definitions (sheet 1 of 2) cr15 cr14 cr13 cr12 cr11 cr10 cr9 cr8 rm asd iad3 iad2 iad1 iad0 doc wc cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 bs cc reserved reserved reserved bl2 bl1 bl0
26 s29cd016g s29cd016_00_a4 november 5, 2004 advance information configuration register cr15 = read mode (rm) 0 = synchronous burst reads enabled 1 = asynchronous reads enabled (default) cr14 = automatic sleep mode disable 0 = automatic sleep mode on (default) 1 = automatic sleep mode off cr13?cr10 = initial burst access delay configuration (iad3-iad0) speed options op, om, oj: 0000 = 2 clk cycle initial burst access delay 0001 = 3 clk cycle initial burst access delay 0010 = 4 clk cycle initial burst access delay 0011 = 5 clk cycle initial burst access delay 0100 = 6 clk cycle initial burst access delay 0101 = 7 clk cycle initial burst access delay 0110 = 8 clk cycle initial burst access delay 0111 = 9 clk cycle initial burst access delay?default cr9 = data output configuration (doc) 0 = hold data for 1-clk cycle?default 1 = reserved cr8 = ind/wait# configuration (wc) 0 = ind/wait# asserted during delay?default 1 = ind/wait# asserted one data cycle before delay cr7 = burst sequence (bs) 0 = reserved 1 = linear burst order?default cr6 = clock configuration (cc) 0 = reserved 1 = burst starts and data output on rising clock edge?default cr5?cr3 = reserved for future enhancements (r) these bits are reserved for future use. set these bits to ?0.? cr2?cr0 = burst length (bl2?bl0) 000 = reserved, burst accesses disabled (asynchronous reads only) 001 = 64 bit (2-double-word) burst data transfer - x32 linear 010 = 128 bit (4-double-word) burst data transfer - x32 linear 011 = 256 bit (8-double-word) burst data transfer - x32 linear (device default) 100 = reserved, burst accesses disabled (asynchronous reads only) 101 = reserved, burst accesses disabled (asynchronous reads only) 110 = reserved, burst accesses disabled (asynchronous reads only) 111 = reserved table 9. configuration register definitions (sheet 2 of 2)
november 5, 2004 s29cd016_00_a4 s29cd016g 27 advance information initial access delay configuration the frequency configuration informs the device of the number of clocks that must elapse after adv# is driven active before data is available. this value is deter- mined by the input clock frequency. sector protection the device features several levels of sect or protection, which can disable both the program and erase operations in certain sectors or sector groups. sector and sector groups the distinction between sectors and sector groups is fundamental to sector pro- tection. sector are individual sectors th at can be individually sector protected/ unprotected. these are the outermost 4 kword boot sectors, that is, sa0 to sa7 and sa38 to sa45. see table 12 on page 34 and table 13 on page 36 . sector groups are a collection of three or four adjacent 32 kword sectors. for ex- ample, sector group sg8 is comprised of sector sa8 to sa10. when any sector in a sector group is protected/unprotected, ev ery sector in that group is protection/ unprotected. see table 12 on page 34 and table 13 on page 36 . persistent sector protection a command sector protection method th at replaces the old 12 v controlled pro- tection method. password sector protection a highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted. wp# hardware protection a write protect pin that can prevent pr ogram or erase to the two outermost 8 kbytes sectors in the 75% bank. all parts default to operate in the pers istent sector protection mode. the cus- tomer must then choose if the persistent or password protection method is most desirable. there are two one-time programmable non-volatile bits that define which sector protection method is used. if the customer decides to continue using the persistent sector protection method, they must set the persistent sector protection mode locking bit . this permanently sets the part to operate only using persistent sector protection. if the customer decides to use the password method, they must set the password mode locking bit . this permanently sets the part to operate only using password sector protection. ta b l e 1 0 . configuration register after device reset cr15 cr14 cr13 cr12 cr11 cr10 cr9 cr8 rm asd iad3 iad2 iad1 iad0 doc wc 10011100 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 bs cc reserve reserve reserve bl2 bl1 bl0 11000100
28 s29cd016g s29cd016_00_a4 november 5, 2004 advance information it is important to remember that setting either the persistent sector protec- tion mode locking bit or the password mode locking bit permanently selects the protection mode. it is not possible to switch between the two methods once a locking bit is set. it is important that one mode is explicitly selected when the device is first programmed, rather than relying on the default mode alone. this is so that it is not possible for a system program or virus to later set the password mode locking bit, which would cause an unexpected shift from the default persistent sector protec tion mode into the password protection mode. the wp# hardware protection feature is always available, independent of the software managed protection method chosen. persistent sector protection the persistent sector protection method replaces the old 12 v controlled protec- tion method while at the same time enhancing flexibility by providing three different sector protection states: ? persistently locked ?a sector is protected and cannot be changed. ? dynamically locked ?the sector is protected and can be changed by a sim- ple command ? unlocked ?the sector is unprotected and can be changed by a simple com- mand in order to achieve these states, three types of ?bits? are going to be used: persistent protection bit (ppb) a single persistent (non-volatile) protection bit is assigned to a maximum of four sectors (see the sector address tables for specific sector protection groupings). all 8 kbyte boot-block sectors have indivi dual sector persistent protection bits (ppbs) for greater flexibility. each ppb is individually modifiable through the ppb write command . note: if a ppb requires erasure, all of the sector ppbs must first be prepro- grammed prior to ppb erasing. all ppbs erase in parallel, unlike programming where individual ppbs are programmable. it is the responsibility of the user to perform the preprogramming operation. otherwise, an already erased sector ppbs includes the potential of being over-erased. there is no hardware mecha- nism to prevent sector ppbs over-erasure. persistent protection bit lock (ppb lock) a global volatile bit. when set to ?1?, the ppbs cannot be changed. when cleared (?0?), the ppbs are changeable. there is only one ppb lock bit per device. the ppb lock is cleared after power-up or hardware reset. there is no command se- quence to unlock the ppb lock. dynamic protection bit (dyb) a volatile protection bit is assigned for each sector. after power-up or hardware reset, the contents of all dybs is ?0?. each dyb is individually modifiable through the dyb write command. when the parts are first shipped, the pp bs are cleared, the dybs are cleared, and ppb lock is defaulted to power up in the cleared state ? meaning the ppbs are changeable. when the device is first powered on the dybs power up cleared (sectors not pro- tected). the protection state for each sector is determined by the logical or of
november 5, 2004 s29cd016_00_a4 s29cd016g 29 advance information the ppb and the dyb related to that sector. for the sectors that have the ppbs cleared, the dybs control whether or not the sector is protected or unprotected. by issuing the dyb write command sequence s, the dybs are set or cleared, thus placing each sector in the protected or unprotected state. these are the so-called dynamic locked or unlocked states. they are called dynamic states because it is very easy to switch back and fo rth between the protected and unprotected conditions. this allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. the dybs maybe set or cleared as often as needed. the ppbs allow for a more static, and difficult to change, level of protection. the ppbs retain their state across power cycles because they are non-volatile. indi- vidual ppbs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. the ppbs are limited to 100 erase cycles. the ppb lock bit adds an additional level of protection. once all ppbs are pro- grammed to the desired settings, the ppb lock may be set to ?1?. setting the ppb lock disables all program and erase comma nds to the non-volatile ppbs. in ef- fect, the ppb lock bit locks the ppbs into their current state. the only way to clear the ppb lock is to go through a power cycle. system boot code can determine if any changes to the ppb are needed e.g. to allow new system code to be down- loaded. if no changes are needed then the boot code can set the ppb lock to disable any further changes to the ppbs during system operation. the wp# write protect pin adds a final le vel of hardware protection to the two outermost 8 kbytes sectors in the 75% bank. when this pin is low it is not pos- sible to change the contents of these two sectors. it is possible to have sectors that are persistently locked, and sectors that are left in the dynamic state. the sectors in the dynamic state are all unprotected. if there is a need to protect some of them, a simple dyb write command sequence is all that is necessary. the dyb write command for the dynamic sectors switch the dybs to signify protected and unprotected, respectively. if there is a need to change the status of the persistently locked sectors, a few more steps are re- quired. first, the ppb lock bit must be disabled by either putting the device through a power-cycle, or hardware reset. the ppbs can then be changed to re- flect the desired settings. setting the ppb lock bit once again locks the ppbs, and the device operates normally again. note: to achieve the best protection, it?s recommended to execute the ppb lock bit set command early in the boot code, and protect the boot code by holding wp# = v il . ta b l e 1 1 . sector protection schemes (sheet 1 of 2) dyb ppb ppb lock sector state 0 0 0 unprotected?ppb and dyb are changeable 0 0 1 unprotected?ppb not changeable, dyb is changeable 010 protected?ppb and dyb are changeable 100 110
30 s29cd016g s29cd016_00_a4 november 5, 2004 advance information ta b l e 1 1 contains all possible combinations of the dyb, ppb, and ppb lock relating to the status of the sector. in summary, if the ppb is set, and the ppb lock is set, the sector is protected and the protection can not be removed until the next power cycle clears the ppb lock. if the ppb is cleared, the sector can be dynamically locked or unlocked. the dyb then controls whether or not the sector is protected or unprotected. if the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. a program command to a protected sec- tor enables status polling for approximatel y 1 s before the device returns to read mode without having modified the contents of the protected sector. an erase command to a protected sector enables status polling for approximately 50 s after which the device returns to read mo de without having erased the protected sector. the programming of the dyb, ppb, and ppb lock for a given sector can be verified by writing a dyb/ppb/ppb lock verify command to the device. persistent sector protection mode locking bit like the password mode locking bit, a pers istent sector protection mode locking bit exists to guarantee that the device remain in software sector protection. once set, the persistent sector protection locking bit prevents programming of the password protection mode locking bit. this guarantees that an unauthorized user could not place the device in password protection mode. password protection mode the password sector protection mode method allows an even higher level of se- curity than the persistent sector protec tion mode. there are two main differences between the persistent sector protection and the password sector protection mode: ? when the device is first powered on, or comes out of a reset cycle, the ppb lock bit set to the locked state , rather than cleared to the unlocked state. ? the only means to clear the ppb lock bit is by writing a unique 64-bit pass- word to the device. the password sector protection method is otherwise identical to the persistent sector protection method. a 64-bit password is the only additional tool utilized in this method. the password is stored in a one-time programmable (otp) region of the flash memory. once the password mode locking bit is set, the password is perma- nently set with no means to read, program, or erase it. the password is used to clear the ppb lock bit. the password unlock command must be written to the flash, along with a password. the flash device internally compares the given password with the pre-programmed password. if they match, the ppb lock bit is cleared, and the ppbs can be altered. if they do not match, the flash device does nothing. there is a built-in 2 s delay for each ?password check.? this delay is 011 protected?ppb not changeable, dyb is changeable 101 111 table 11. sector protection schemes (sheet 2 of 2) dyb ppb ppb lock sector state
november 5, 2004 s29cd016_00_a4 s29cd016g 31 advance information intended to thwart any efforts to run a program that tries all possible combina- tions in order to crack the password. password and password mode locking bit in order to select the password sector protection scheme, the customer must first program the password. one method of choosing a password would be to correlate it to the unique electronic serial number (esn) of the particular flash device. an- other method could generate a database where all the passwords are stored, each of which correlates to a serial number on the device. each esn is different for every flash device; therefore each password should be different for every flash device. while programming in the passw ord region, the customer may perform password verify operations. once the desired password is programmed in, the customer must then set the password mode locking bit. this operation achieves two objectives: 1) it permanently sets the device to operate using the password protection mode. it is not possible to reverse this function. 2) it also disables all further commands to the password region. all program, and read operations are ignored. both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. the user must be sure that the password protection method is desired when setting the passwo rd mode locking bit. more importantly, the user must be sure that the password is correct when the password mode locking bit is set. due to the fact that read operations are disabled, there is no means to verify what the password is aft erwards. if the password is lost after set- ting the password mode locking bit, there is no way to clear the ppb lock bit. the password mode locking bit, once set, prevents reading the 64-bit password on the dq bus and further password programming. the password mode locking bit is not erasable. once password mode locking bit is programmed, the persis- tent sector protection locking bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 64-bit password the 64-bit password is located in its own memory space and is accessible through the use of the password program and verify commands (see ?password verify command? on page 53 ). the password function works in conjunction with the password mode locking bit, which when set, prevents the password verify com- mand from reading the contents of the password on the pins of the device.
32 s29cd016g s29cd016_00_a4 november 5, 2004 advance information write protect (wp#) the device features a hardware protection option using a write protect pin that prevents programming or erasing, regardless of the state of the sector?s persis- tent or dynamic protection bits. the wp# pin is associated with the two outermost 8kbytes sectors in the 75% bank. the wp# pin has no effect on any other sector. when wp# is taken to v il , programming and erase operations of the two outermost 8 kbytes sectors in the 75% bank are disabled. by taking wp# back to v ih , the two outermost 8 kbytes sectors are enabled for program and erase operations, depending upon the status of the individual sector persistent or dynamic protection bits. if either of the two outermost sectors persistent or dy- namic protection bits are programmed, program or erase operations are inhibited. if the sector persistent or dy namic protection bits are both erased, the two sectors are available for programming or erasing as long as wp# remains at v ih . the user must hold the wp# pin at either v ih or v il during the entire pro- gram or erase operation of the two outermost sectors in the 75% bank. secsi? (secured silicon) sector protection the secsi sector is a 256-byte flash me mory area that is either programmable at the customer or by amd at the request of the customer. the secsi sector entry command enables the host system to a ddress the secsi sector for programming or reading. the secsi sector address range is 00000h?0003fh for the ordering option 00 and 7ffc0h?7ffffh for the ordering option 01. address range 00040h?007ffh for ordering option 0 and 7f 800h?7ffbfh for ordering option 01 return invalid data when addressed with the secsi sector enabled. the device allows simultaneous read/write operation while the secsi sector is enabled. however, there are a number of restrictions associated with simulta- neous read/write operations and device operation when the secsi sector is enabled: 1) the secsi sector is not available for reading while the password unlock, any ppb program/erase operation, or password programming are in progress. reading to any location in the small (25%) sector returns the status of these operations until these operations have completed execution. 2) writing the corresponding dyb associated with the overlaid bootblock sector results in the dyb not being updated. this is only accomplished when the secsi sector is not enabled. 3) reading the corresponding dyb associated with the overlaid bootblock sector results in reading invalid data when th e ppb lock/dyb verify command is is- sued. this function is only accomplished when the secsi sector is not enabled. 4) all commands are available for execut ion when the secsi sector is enabled except the following list. issuing the following commands while the secsi sector is enabled results in the command being ignored. ? all unlock bypass commands ? cfi ? accelerated program ? program and sector erase suspend ? program and sector erase resume 5) executing the sector erase command is permitted when the secsi sector is enabled, however, there is no provision for erasing the secsi sector with the
november 5, 2004 s29cd016_00_a4 s29cd016g 33 advance information sector erase command, regardless of the protection status. the sector erase command erases all other sectors when the secsi sector is enabled. 6) executing the chip erase command is permitted when the secsi sector is en- abled. the chip erase command erases all sectors in the memory array except for sector 0 in top-bootblock configuration and sector 45 in bottom- bootblock configuration. the secsi sector is a one-time programmable mem- ory area that cannot be erased. 7) executing the secsi sector entry command during program or erase suspend mode is allowed. the sector erase/program resume command is disabled while the secsi sector is enabled, and the user cannot resume programming of the memory array until the exit secsi sector command is written. secsi sector protection bit the secsi sector protection bit prevents programming of the secsi sector mem- ory area. once set, the secsi sector me mory area contents are non-modifiable. persistent protection bit lock the persistent protection bit (ppb) lock is a volatile bit that reflects the state of the password mode locking bit after power-up reset. if the password mode lock- ing bit is set, which indicates the device is in password protection mode, the ppb lock bit is also set after a hardware reset (reset# asserted) or a power-up reset. the only means for clearing the ppb lock bit in password protection mode is to issue the password unlock command. successful execution of the password un- lock command clears the ppb lock bit, allowing for sector ppbs modifications. asserting reset#, taking the device through a power-on reset, or issuing the ppb lock bit set command sets the ppb lock bit back to a ?1?. if the password mode locking bit is not set, indicating persistent sector protec- tion mode, the ppb lock bit is cleared after power-up or hardware reset. the ppb lock bit is set by issuing the ppb lock bit set command. once set the only means for clearing the ppb lock bit is by issuing a hardware or power-up reset. the password unlock command is ignored in persistent sector protection mode. hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadve rtent writes. in addition, the following hardware data protection measures preven t accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this pro- tects data during v cc power-up and power-down. the command register and all internal erase/program circuits are disa bled, and the device resets. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce#, or we# do not initiate a write cycle.
34 s29cd016g s29cd016_00_a4 november 5, 2004 advance information logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih , or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero (v il ) while oe# is a logical one (v ih ). power-up write inhibit if we# = ce# = v il and oe# = v ih during power-up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to reading array data on power-up. v cc and v io power-up and power-down sequencing the device imposes no restrictions on v cc and v io power-up or power-down se- quencing. asserting reset# to v il is required during the entire v cc and v io power sequence until the respective su pplies reach their operating voltages. once, v cc and v io attain their respective operatin g voltages, de-assertion of re- set# to v ih is permitted. table 12. sector addresses for ordering option 00 (sheet 1 of 2) sector sector group x32 address range (a18:a0) sector size (kdwords) bank 0 (note 2) sa0 (note 1) sg0 00000h?007ffh 2 sa1 sg1 00800h?00fffh 2 sa2 sg2 01000h?017ffh 2 sa3 sg3 01800h?01fffh 2 sa4 sg4 02000h?027ffh 2 sa5 sg5 02800h?02fffh 2 sa6 sg6 03000h?037ffh 2 sa7 sg7 03800h?03fffh 2 sa8 sg8 04000h?07fffh 16 sa9 08000h?0bfffh 16 sa10 0c000h?0ffffh 16 sa11 sg9 10000h?13fffh 16 sa12 14000h?17fffh 16 sa13 18000h?1bfffh 16 sa14 1c000h?1ffffh 16
november 5, 2004 s29cd016_00_a4 s29cd016g 35 advance information 1. secsi sector overlays this sector when enabled. 2. the bank address is determined by a18 and a17. ba = 00 for bank 1 and ba = 01, 10, or 11 for bank 2. 3. this sector includes the additional wp# pin sector protection feature. bank 1 (note 2) sa15 sg10 20000h?23fffh 16 sa16 24000h?27fffh 16 sa17 28000h?2bfffh 16 sa18 2c000h?2ffffh 16 sa19 sg11 30000h?33fffh 16 sa20 34000h?37fffh 16 sa21 38000h?3bfffh 16 sa22 3c000h?3ffffh 16 sa23 sg12 40000h?43fffh 16 sa24 44000h?47fffh 16 sa25 48000h?4bfffh 16 sa26 4c000h?4ffffh 16 sa27 sg13 50000h?53fffh 16 sa28 54000h?57fffh 16 sa29 58000h?5bfffh 16 sa30 5c000h?5ffffh 16 sa31 sg14 60000h?63fffh 16 sa32 64000h?67fffh 16 sa33 68000h?6bfffh 16 sa34 6c000h?6ffffh 16 sa35 sg15 70000h?73fffh 16 sa36 74000h?77fffh 16 sa37 78000h?7bfffh 16 sa38 sg16 7c000h?7c7ffh 2 sa39 sg17 7c800h?7cfffh 2 sa40 sg18 7d000h?7d7ffh 2 sa41 sg19 7d800h?7dfffh 2 sa42 sg20 7e000h?7e7ffh 2 sa43 sg21 7e800h?7efffh 2 sa44 (note 3) sg22 7f000h?7f7ffh 2 sa45 (note 3) sg23 7f800h?7ffffh 2 table 12. sector addresses for ordering option 00 (sheet 2 of 2) sector sector group x32 address range (a18:a0) sector size (kdwords)
36 s29cd016g s29cd016_00_a4 november 5, 2004 advance information table 13. sector addresses for ordering option 01 (sheet 1 of 2) sector sector group x32 address range (a18:a0) sector size (kdwords) bank 0 (note 2) sa0 (note 1) sg0 00000h?007ffh 2 sa1 (note 1) sg1 00800h?00fffh 2 sa2 sg2 01000h?017ffh 2 sa3 sg3 01800h?01fffh 2 sa4 sg4 02000h?027ffh 2 sa5 sg5 02800h?02fffh 2 sa6 sg6 03000h?037ffh 2 sa7 sg7 03800h?03fffh 2 sa8 sg8 04000h?07fffh 16 sa9 08000h?0bfffh 16 sa10 0c000h?0ffffh 16 sa11 sg9 10000h?13fffh 16 sa12 14000h?17fffh 16 sa13 18000h?1bfffh 16 sa14 1c000h?1ffffh 16 sa15 sg10 20000h?23fffh 16 sa16 24000h?27fffh 16 sa17 28000h?2bfffh 16 sa18 2c000h?2ffffh 16 sa19 sg11 30000h?33fffh 16 sa20 34000h?37fffh 16 sa21 38000h?3bfffh 16 sa22 3c000h?3ffffh 16 sa23 sg12 40000h?43fffh 16 sa24 44000h?47fffh 16 sa25 48000h?4bfffh 16 sa26 4c000h?4ffffh 16 sa27 sg13 50000h?53fffh 16 sa28 54000h?57fffh 16 sa29 58000h?5bfffh 16 sa30 5c000h?5ffffh 16
november 5, 2004 s29cd016_00_a4 s29cd016g 37 advance information 1. this sector includes the additional wp# pin sector protection feature. 2. the bank address is determined by a18 and a17. ba = 00, 01, or 10 for bank 0 and ba = 11 for bank 1. 3. secsi sector overlays this sector when enabled. bank 1 (note 2) sa31 sg14 60000h?63fffh 16 sa32 64000h?67fffh 16 sa33 68000h?6bfffh 16 sa34 6c000h?6ffffh 16 sa35 sg15 70000h?73fffh 16 sa36 74000h?77fffh 16 sa37 78000h?7bfffh 16 sa38 sg16 7c000h?7c7ffh 2 sa39 sg17 7c800h?7cfffh 2 sa40 sg18 7d000h?7d7ffh 2 sa41 sg19 7d800h?7dfffh 2 sa42 sg20 7e000h?7e7ffh 2 sa43 sg21 7e800h?7efffh 2 sa44 sg22 7f000h?7f7ffh 2 sa45 (note 3) sg23 7f800h?7ffffh 2 table 13. sector addresses for ordering option 01 (sheet 2 of 2) sector sector group x32 address range (a18:a0) sector size (kdwords)
38 s29cd016g s29cd016_00_a4 november 5, 2004 advance information common flash memory interface (cfi) the common flash interface (cfi) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified soft- ware algorithms to be used for entire families of devices. software support can then be device-independent, jedec id -independent, and forward- and back- ward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h in word mode (or address aah in byte mode), any time the device is ready to read array data. the system can read cfi information at the addresses given in table 14 on page 38 to ttable 17 on page 41 . to ter- minate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the au- toselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in table 14 on page 38 to ttable 17 on page 41 . the system must write the reset command to return the device to the autoselect mode. for further information, please refer to the cfi specification and cfi publication 100, available via the world wide web at http://www.amd.com/products/nvd/ overview/cfi.html. alternatively, contact a spansion representative for copies of these documents. note: cfi cannot be read in synchronous mode. ta b l e 1 4 . cfi query identification string addresses data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists)
november 5, 2004 s29cd016_00_a4 s29cd016g 39 advance information ta b l e 1 5 . cfi system interface string addresses data description 1bh 0023h v cc min. (write/erase) dq7?dq4: volts, dq3?dq0: 100 millivolt 1ch 0027h v cc max. (write/erase) dq7?dq4: volts, dq3?dq0: 100 millivolt 1dh 0000h v pp min. voltage (00h = no v pp pin present) 1eh 0000h v pp max. voltage (00h = no v pp pin present) 1fh 0004h typical timeout per single word/doubleword program 2 n s 20h 0000h typical timeout for min. size buffer program 2 n s (00h = not supported) 21h 0009h typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0005h max. timeout for word/doubleword program 2 n times typical 24h 0000h max. timeout for buffer write 2 n times typical 25h 0007h max. timeout per individual block erase 2 n times typical 26h 0000h max. timeout for full chip erase 2 n times typical (00h = not supported)
40 s29cd016g s29cd016_00_a4 november 5, 2004 advance information table 16. device geometry definition addresses data description 27h 0015h device size = 2 n byte 28h 29h 0003h 0000h flash device interface description (for complete description, please refer to cfi publication 100) 0000 = x8-only asynchronous interface 0001 = x16-only asynchronous interface 0002 = supports x8 and x16 via byte# with asynchronous interface 0003 = x 32-only asynchronous interface 2ah 2bh 0000h 0000h max. number of byte in multi-byte program = 2 n (00h = not supported) 2ch 0003h number of erase block regions within device 2dh 2eh 2fh 30h 0007h 0000h 0020h 0000h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 32h 33h 34h 001dh 0000h 0000h 0001h erase block region 2 information (refer to the cfi specification or cfi publication 100) 35h 36h 37h 38h 0007h 0000h 0020h 0000h erase block region 3 information (refer to the cfi specification or cfi publication 100) 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information (refer to the cfi specification or cfi publication 100)
november 5, 2004 s29cd016_00_a4 s29cd016g 41 advance information ta b l e 1 7 . cfi primary vendor-specific extended query (sheet 1 of 2) addresses data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 0031h major version number, ascii (reflects modifications to the silicon) 44h 0033h minor version number, ascii (reflects modifications to the cfi table) 45h 0004h address sensitive unlock (dq1, dq0) 00 = required, 01 = not required silicon revision number (dq5?dq2 0000 = cs49 0001 = cs59 0010 = cs99 0011 = cs69 0100 = cs119 46h 0002h erase suspend (1 byte) 00 = not supported 01 = to read only 02 = to read and write 47h 0001h sector protect (1 byte) 00 = not supported, x = number of sectors in per group 48h 0000h temporary sector unprotect 00h = not supported, 01h = supported 49h 0006h sector protect/unprotect scheme (1 byte) 01 =29f040 mode, 02 = 29f016 mode 03 = 29f400 mode, 04 = 29lv800 mode 05 = 29bds640 mode (software command locking) 06 = bdd160 mode (new sector protect) 07 = 29lv800 + pdl128 (new sector protect) mode 4ah 001fh simultaneous read/write (1 byte) 00h = not supported, x = number of sectors in all banks except bank 1 4bh 0001h burst mode type 00h = not supported, 01h = supported 4ch 0000h page mode type 00h = not supported, 01h = 4 word page, 02h = 8 word page 4dh 00b5h acc (acceleration) supply minimum 00h = not supported (dq7-dq4: volt in hex, dq3-dq0: 100 mv in bcd) 4eh 00c5h acc (acceleration) supply maximum 00h = not supported, (dq7-dq4: volt in hex, dq3-dq0: 100 mv in bcd)
42 s29cd016g s29cd016_00_a4 november 5, 2004 advance information 4fh 0001h top/bottom boot sector flag (1 byte) 00h = uniform device, no wp# control, 01h = 8 x 8 kb sectors at top and bottom with wp# control 02h = bottom boot device 03h = top boot device 04h = uniform, bottom wp# protect 05h = uniform, top wp# protect if the number of erase block regions = 1, then ignore this field 50h 0001h program suspend 00 = not supported 01 = supported 51h 0000h write buffer size 2 (n+1) word(s) 57h 0002h bank organization (1 byte) 00 = if data at 4ah is zero xx = number of banks 58h 000fh bank 1 region information (1 byte) xx = number of sectors in bank 1 59h 001fh bank 2 region information (1 byte) xx = number of sectors in bank 2 5ah 0000h bank 3 region information (1 byte) xx = number of sectors in bank 3 5bh 0000h bank 4 region information (1 byte) xx = number of sectors in bank 4 table 17. cfi primary vendor-specific extended query (sheet 2 of 2) addresses data description
november 5, 2004 s29cd016_00_a4 s29cd016g 43 advance information command definitions writing specific address and data commands or sequences into the command register initiates device operations. tables 8 - 9 define the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to ?ac characteristics? on page 70 for timing diagrams. reading array data in non-burst mode the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. th e device is also ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase suspend mode. the system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. after completing a programming operation in the erase sus- pend mode, the system may once again rea d array data with the same exception. see ?sector erase and program suspend command? on page 49 for more infor- mation on this mode. the system must issue the reset command to re- enable the device for reading array data if dq5 goes high, or while in the autoselect mode. see also ?asynchronous read operation (non-burst)? on page 19 for more information. see ?sector erase and program resume command? on page 51 for more information on this mode. reading array data in burst mode the device is capable of very fast burs t mode read operations. the configuration register sets the read configuration, burst order, frequency configuration, and burst length. upon power on, the device defaults to the asynchronous mode. in this mode, clk, and adv# are ignored. the device operates like a conventional flash device. data is available t acc /t ce nanoseconds after address becomes stable, ce# be- come asserted. the device enters the bu rst mode by enabling synchronous burst reads in the configuration register. the de vice exits burst mode by disabling syn- chronous burst reads in the configuration register. (see ?command definitions? on page 43 ). the reset# command does not terminate the burst mode. system reset (power on reset) term inates the burst mode. the device contains the regular control pins, i.e. chip enable (ce#), write enable (we#), and output enable (oe#) to control normal read and write operations. moreover, three additional control pins w ere added to allow easy interface with minimal glue logic to a wide range of microprocessors / microcontrollers for high performance burst read capability. these additional pins are address valid (adv#) and clock (clk). ce#, oe#, and we# are asynchronous (relative to clk). the burst mode read operation is a synchronous operation tied to the edge of the clock. the microprocessor / microcontroller supplies only the initial ad- dress, all subsequent addresses are automatically generated by the device with a timing defined by the configuration register definition. the burst read cycle consists of an address phase and a corresponding data phase.
44 s29cd016g s29cd016_00_a4 november 5, 2004 advance information during the address phase, the address valid (adv#) pin is asserted (taken low) for one clock period. together with the edge of the clk, the starting burst address is loaded into the internal burst address counter. the internal burst address counter can be configured to either the linear modes (see ?initial access delay configuration? on page 27 ). during the data phase, the fi rst burst data is available after the initial access time delay defined in the configuration register. for subsequent burst data, every ris- ing (or falling) edge of the clk triggers the output data with the burst output delay and sequence defined in the configuration register. tables 8?9 show all the commands executed by the device. the device automat- ically powers up in the read/reset state. it is not necessary to issue a read/reset command after power-up or hardware reset. read/reset command after power-up or hardware reset, the device automatically enter the read state. it is not necessary to issue the reset command after power-up or hardware reset. standard microprocessor cycles retrieve array data, however, after power-up, only asynchronous accesses are permitted since the configuration register is at its reset state with bu rst accesses disabled. the reset command is executed when the user needs to exit any of the other user command sequences (such as autoselect, pr ogram, chip erase, etc.) to return to reading array data. there is no latenc y between executing the reset command and reading array data. the reset command does not disable the secsi sector if it is enabled. this func- tion is only accomplished by issuing the secsi sector exit command. autoselect command flash memories are intended for use in applications where the local cpu alters memory contents. as such, manufacturer and device codes must be accessible while the device resides in the target system. prom programmers typically ac- cess the signature codes by raising a9 to v id . however, multiplexing high voltage onto the address lines is not generally desired system design practice. the device contains an autoselect command operation to supplement traditional prom programming methodology. the operation is initiated by writing the au- toselect command sequence into the command register. the bank address (ba) is latched during the autoselect command sequence write operation to distinguish which bank the autoselect command references. reading the other bank after the autoselect command is written results in reading array data from the other bank and the specified address. following th e command write, a read cycle from ad- dress (ba)xx00h retrieves the manuf acturer code of (ba)xx01h. three sequential read cycles at addresses (ba) xx01h, (ba) xx0eh, and (ba) xx0fh read the three-byte device id (see table 8). (the autoselect command requires the user to execute the read/reset command to return the device back to reading the array contents.) program command sequence programming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write cycl es, followed by the program set-up com- mand. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further con-
november 5, 2004 s29cd016_00_a4 s29cd016g 45 advance information trols or timings. the device automati cally generates the program pulses and verifies the programmed cell margin. tables 8 and 9 show the address and data requirements for the program command sequence. during the embedded program algorithm, the system can determine the status of the program operation by using dq7, dq6, or ry/by#. (see ?write operation status? on page 60 for information on these status bits.) when the embedded program algorithm is complete, the device returns to reading array data and ad- dresses are no longer latched. note that an address change is required to begin read valid array data. except for program suspend, any commands written to the device during the em- bedded program algorithm are ignored. note that a hardware reset immediately terminates the programming operation. the command sequence should be reinitiated once that bank returns to reading array data, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a ?0? back to a ?1?. attempting to do so may halt the operation and set dq5 to ?1,? or cause the data# polling algorithm to indicate the operation was successful. however, a succeeding read shows that the data is still ?0?. only erase operations can convert a ?0? to a ?1?. accelerated program command the accelerated chip program mode is designed to improve the word or double word programming speed. improving the programming speed is accomplished by using the acc pin to supply both the wordline voltage and the bitline current in- stead of using the v pp pump and drain pump, which is limited to 2.5 ma. because the external acc pin is capable of supplyi ng significantly large amounts of current compared to the drain pump, all 32 bits are available for programming with a sin- gle programming pulse. this is an enormous improvement over the standard 5- bit programming. if the user is able to supply an external power supply and con- nect it to the acc pin, signif icant time savings are realized. in order to enter the accelerated progra m mode, the acc pin must first be taken to v hh (12 v 0.5 v) and followed by the one-cycle command with the program address and data to follow. the accelerated chip program command is only exe- cuted when the device is in unlock by pass mode and during normal read/reset operating mode. in this mode, the write protection function is bypassed unless the ppb lock bit = 1. the accelerated program command is not permitted if the secsi sector is enabled. unlock bypass command sequence the unlock bypass feature allows the system to program words to the device faster than using the standard program command sequence. the unlock bypass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. the device then enters the unlock bypass mode. a two-cycle unlock bypass program com- mand sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required
46 s29cd016g s29cd016_00_a4 november 5, 2004 advance information in the standard program command sequence, resulting in faster total program- ming time. figure 19, on page 58 and figure 20, on page 59 show the requirements for the command sequence. during the unlock bypass mode, only the unlock bypass program and unlock by- pass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. the first cycle must contain the data 90h; the second cycle the data 00h. addresses are don?t care for both cycles. the device th en returns to reading array data. figure 4 illustrates the algorithm for the program operation. see table 29 on page 85 for parameters, and figure 21, on page 78 and figure 22, on page 79 for timing diagrams. unlock bypass entry command the unlock bypass command, once issued, is used to bypass the ?unlock? se- quence for program, chip erase, and cfi commands. this feature permits slow prom programmers to significantly improve programming/erase throughput since the command sequence often requires microseconds to execute a single write operation. therefore, once the unlo ck bypass command is issued, only the two-cycle program and erase bypass comma nds are required. the unlock bypass command is ignored if the secsi sector is enabled. to return back to normal op- eration, the unlock bypass reset command must be issued. start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress n ote: see tables 8 and 9 for program command sequence. figure 4. program operation
november 5, 2004 s29cd016_00_a4 s29cd016g 47 advance information the following four sections describe the commands that may be executed within the unlock bypass mode. unlock bypass program command the unlock bypass program command is a two-cycle command that consists of the actual program command (a0h) and the program address/data combination. this command does not require the two-cycl e ?unlock? sequence since the unlock bypass command was previously issued. as with the standard program com- mand, multiple unlock bypass program commands can be issued once the unlock bypass command is issued. to return back to standard read operat ions, the unlock bypass reset command must be issued. the unlock bypass program command is ignored if the secsi sector is enabled. unlock bypass chip erase command the unlock bypass chip erase command is a 2-cycle command that consists of the erase setup command (80h) and the actual chip erase command (10h). this command does not require the two-cycle ? unlock? sequence since the unlock by- pass command was previously issued. unlike the standard erase command, there is no unlock bypass erase suspend or erase resume commands. to return back to standard read operat ions, the unlock bypass reset command must be issued. the unlock bypass program command is ignored if the secsi sector is enabled. unlock bypass cfi command the unlock bypass cfi command is availa ble for prom programmers and target systems to read the cfi codes while in unlock bypass mode. see ?common flash interface (cfi) command? on page 51 for specific cfi codes. to return back to standard read operat ions, the unlock bypass reset command must be issued. the unlock bypass program command is ignored if the secsi sector is enabled. unlock bypass reset command the unlock bypass reset command places the device in standard read/reset op- erating mode. once executed, normal read operations and user command sequences are available for execution. the unlock bypass program command is ignored if the secsi sector is enabled. chip erase command the chip erase command is used to eras e the entire flash memory contents of the chip by issuing a single command. chip erase is a six-bus cycle operation. there are two ?unlock? write cycles, follo wed by writing the erase ?set up? com- mand. two more ?unlock? write cycles are followed by the chip erase command. chip erase does not erase protected sectors. the chip erase operation initiates the embedded erase algorithm, which automat- ically preprograms and verifies the entire memory to an all zero pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. note that a hardware reset immediately terminates
48 s29cd016g s29cd016_00_a4 november 5, 2004 advance information the programming operation. the command sequence should be reinitiated once that bank returns to reading array data, to ensure data integrity. the embedded erase algorithm erase begins on the rising edge of the last we# or ce# pulse (whichever occurs first) in the command sequence. the status of the erase operation is determined three ways: ? data# polling of the dq7 pin (see ?dq7: data# polling? on page 60 ) ? checking the status of the toggle bit dq6 (see ?dq6: toggle bit i? on page 62 ) ? checking the status of the ry/by# pin (see ?ry/by#: ready/busy#? on page 62 ) once erasure starts, only the erase suspend command is valid. all other com- mands are ignored. when the embedded erase algorithm is co mplete, the device returns to reading array data, and addresses are no longer latched. note that an address change is required to begin read valid array data. figure 5, on page 49 illustrates the embedded erase algorithm. see table 27 on page 77 for parameters, and figure 21, on page 78 and figure 22, on page 79 for timing diagrams. sector erase command the sector erase command is used to eras e individual sectors or the entire flash memory contents. sector erase is a si x-bus cycle operation. there are two ?un- lock? write cycles, followed by writing the erase ?set up? command. two more ?unlock? write cycles are then followed by the erase command (30h). the sector address (any address location within the desired sector) is latched on the falling edge of we# or ce# (whichever occurs last) while the command (30h) is latched on the rising edge of we# or ce# (whichever occurs first). specifying multiple sectors for erase is accomplished by writing the six bus cycle operation, as described above, and then following it by additional writes of only the last cycle of the sector erase command to addresses or other sectors to be erased. the time between sector erase command writes must be less than 80 s, otherwise the command is rejected. it is recommended that processor interrupts be disabled during this time to guarantee this critical timing condition. the inter- rupts can be re-enabled after the last se ctor erase command is written. a time- out of 80 s from the rising edge of the last we# (or ce#) initiates the execution of the sector erase command(s). if another falling edge of the we# (or ce#) oc- curs within the 80 s time-out window, the timer is reset. once the 80 s window times out and erasure starts, only the erase suspend command is recognized (see ?sector erase and program suspend command? on page 49 and ?sector erase and program resume command? on page 51 ). if that occurs, the sector erase command sequence should be reinitiat ed once that bank returns to reading array data, to ensure data integrity. lo ading the sector erase registers may be done in any sequence and with any number of sectors. sector erase does not require the user to program the device prior to erase. the device automatically preprograms all memory locations, within sectors to be erased, prior to electrical erase. when erasing a sector or sectors, the remaining unselected sectors or the write protected sectors are unaffected. the system is not required to provide any controls or timings during sector erase operations. the erase suspend and erase resume commands may be written as often as re- quired during a sector erase operation.
november 5, 2004 s29cd016_00_a4 s29cd016g 49 advance information automatic sector erase operations begin on the rising edge of the we# or ce# pulse of the last sector erase command issued, and once the 80 s time-out win- dow expires. the status of the sector er ase operation is determined three ways: ? data# polling of the dq7 pin ? checking the status of the toggle bit dq6 ? checking the status of the ry/by# pin further status of device activity during the sector erase operation is determined using toggle bit dq2 (refer to ?dq2: toggle bit ii? on page 63 ). when the embedded erase algorithm is co mplete, the device returns to reading array data, and addresses are no longer latched. note that an address change is required to begin read valid array data. figure 5 illustrates the embedded? erase al gorithm, using a typical command sequence and bus operation. refer to table 29 on page 85 for parameters, and figure 21, on page 78 and figure 22, on page 79 for timing diagrams. sector erase and program suspend command the sector erase and program suspend command allows the user to interrupt a sector erase or program operation and perform data read or programs in a sector that is not being erased or to the sector where a programming operation was ini- tiated. this command is applicable only during the sector erase and programming operation, which includes the time-out period for sector erase. start write erase command sequence data poll from system data = ffh? no yes erasure completed embedded erase algorithm in progress notes: 1. see table 27 on page 77 and table 28 on page 83 for erase command sequence. 2. see ?dq3: sector erase timer? on page 65r for more information. figure 5. erase operation
50 s29cd016g s29cd016_00_a4 november 5, 2004 advance information sector erase and program suspend operation mechanics the sector erase and program suspend command is ignored if written during the execution of the chip erase operation or embedded program algorithm (but re- sets the chip if written improperly during the command sequences). writing the sector erase and program command during the sector erase time-out results in immediate termination of the time-out period and suspension of the erase oper- ation. once in erase suspend, the device is available for reading (note that in the erase suspend mode, the reset command is not required for read operations and is ignored) or program operations in sectors not being erased. any other com- mand written during the erase suspend mode is ignored, except for the sector erase and program resume command. writing the erase and program resume command resumes the sector erase operation. the bank address of the erase suspended bank is required when writing this command if the sector erase and program suspend command is written during a program- ming operation, the device suspends programming operations and allows only read operations in sectors not selected for programming. further nesting of either erase or programming operations is not permitted. ta b l e 1 8 summarizes permis- sible operations during erase and program suspend. (a busy sector is one that is selected for programming or erasure.) ta b l e 1 8 . allowed operations during erase/program suspend when the sector erase and program suspend command is written during a sector erase operation, the chip takes between 0. 1 s and 20 s to actually suspend the operation and go into the erase suspended read mode (pseudo-read mode), at which time the user can read or program from a sector that is not erase sus- pended. reading data in this mode is the same as reading from the standard read mode, except that the data must be read from sectors that have not been erase suspended. polling dq6 on two immediately consecutive reads from a given address provides the system with the ability to determine if the device is in erase or program sus- pend. before the device enters erase or program suspend, the dq6 pin toggles between two immediately consecutive reads from the same address. after the device enters erase suspend, dq6 stops toggling between two immediately con- secutive reads to the same address. during the sector erase operation and also in erase suspend mode, two immediatel y consecutive readings from the erase- suspended sector causes dq2 to toggle. dq2 does not toggle if reading from a non-busy (non-erasing) sector (stored data is read). no bits are toggled during program suspend mode. software must keep track of the fact that the device is in a suspended mode. after entering the erase-suspend-read mode, the system may read or program within any non-suspended sector: ? a read operation from the erase-suspended bank returns polling data up to 20 s after the erase suspend command is issued; read operations thereafter return array data. read operations from the other bank return array data with no latency. sector program suspend erase suspend busy sector program resume erase resume non-busy sectors read only read or program
november 5, 2004 s29cd016_00_a4 s29cd016g 51 advance information ? a program operation while in the erase suspend mode is the same as pro- gramming in the regular program mode, except that the data must be pro- grammed to a sector that is not erase suspended. write operation status is obtained in the same manner as a normal program operation. sector erase and program resume command the sector erase and program resume command (30h) resumes a sector erase or program operation that was suspended. any further writes of the sector erase and program resume command ignored. however, another sector erase and pro- gram suspend command can be written after the device resumes sector erase operations. note that until a suspended program or erase operation resumes, the contents of that sector are unknown. the sector erase and program resume command is ignored if the secsi sector is enabled. configuration register read command the configuration register read command is used to verify the contents of the configuration register. execution of this command is only allowed while in user mode and is not available during unlock bypass mode or during security mode. the configuration register read command is preceded by the standard two-cycle ?unlock? sequence, followed by the configuration register read command (c6h), and finally followed by performing a read operation to the bank address specified when the c6h command was written. read ing the other bank results in reading the flash memory contents. the contents of the configuration register are place on dq15?dq0. the contents of dq31?dq16 are xxxxh and should be ignored. the user should execute the read/reset command to place the device back in standard user operation after executing the configuration register read command. the configuration register read command is fully operational if the secsi sector is enabled. configuration register write command the configuration register write command is used to modify the contents of the configuration register. execution of this command is only allowed while in user mode and is not available during unlock bypass mode or during security mode. the configuration register write command is preceded by the standard two-cycle ?unlock? sequence, followed by the configuration register write command (d0h), and finally followed by writing the contents of the configuration register to any address. the contents of the configurat ion register are place on dq31?dq0. the contents of dq31?dq16 are xxxxh and are ignored. writing the configuration register while an embedded algorithm? or erase suspend modes are executing results in the contents of the configuration register not being updated. the configuration register read command is fully operational if the secsi sector is enabled. common flash interface (cfi) command the common flash interface (cfi) command provides device size, geometry, and capability information directly to the users system. flash devices that support cfi, have a ?query command? that returns information about the device to the system. the query structure contents are read at the specific address locations following a single system write cycle where:
52 s29cd016g s29cd016_00_a4 november 5, 2004 advance information ? a 98h query command code is written to 55h address location within the de- vice?s address space ? the device is initially in any valid read state, such as ?read array? or ?read id data? other device statistics may exist within a long sequence of commands or data in- put; such sequences must first be completed or terminated before writing of the 98h query command, otherwise invalid qu ery data structure output may result. note that for data bus bits greater than dq7 (dq31?dq8), the valid query access code contains all zeroes (?0?s) in the upper dq bus locations. thus, the 16-bit query command code is 0098h and the 32-bit query command code is 00000098h. to terminate the cfi operation, it is necessary to execute the read/reset command. the cfi command is not permitted if the secsi sector is enabled and simulta- neous read/write operation is disa bled once the command is entered. see ?common flash interface (cfi) command? on page 51 for the specific cfi command codes. secsi sector entry command the secsi sector entry command enables the secsi (otp) sector to overlay the 8 kb outermost sector in the small (25%) bank. the secsi sector overlays 00000h?0003fh for the top bootblock configuration and 7ffc0h?7ffffh for the bottom bootblock configuration. address range 00040h?007ffh for the top boot- block and 7f800h?7ffbfh return invalid data when addressed with the secsi sector enabled. the following commands are permitted after issuing the secsi sector entry command: 1. autoselect 2. password program 3. password verify 4. password unlock 5. read/reset 6. program 7. chip and sector erase 8. secsi sector protection bit program 9. ppb program 10. all ppb erase 11. ppb lock bit set 12. dyb write 13. dyb/ppb/ppb lock bit verify 14. security reset 15. configuration register write 16. configuration register read the following commands are unavailable when the secsi sector is enabled. issu- ing the following commands while the secsi sector is enabled results in the command being ignored. 1. unlock bypass 2. cfi 3. accelerated program
november 5, 2004 s29cd016_00_a4 s29cd016g 53 advance information 4. program and sector erase suspend 5. program and sector erase resume the secsi sector entry command is allowed when the device is in either program or erase suspend modes. if the secsi sector is enabled, the program or erase sus- pend command is ignored. this prevents resuming either programming or erasure on the secsi sector if the overl ayed sector was undergoing programming or erasure. the host system must ensure that the device resume any sus- pended program or erase operation after exiting the secsi sector . executing any of the ppb program/erase commands, or password unlock com- mand results in the small bank (25% bank) returning the status of these operations while they are in progress, th us making the secsi sector unavailable for reading. if the secsi sector is enabled while the dyb command is issued, the dyb for the overlayed sector is not updated. reading the dyb status using the ppb lock bit/dybdyb verify command when the secsi sector is enabled returns invalid data. password program command the password program command permits programming the password that is used as part of the hardware protection scheme. the actual password is 64-bits long. depending upon the state of the word# pin, multiple password program commands are required. for a x32 bit data bus, 2 password program commands are required. the user must enter the un lock cycle, password program command (38h) and the program address/data for each portion of the password when pro- gramming. there are no provisions for entering the 2-cycle unlock cycle, the password program command, and all the password data. there is no special ad- dressing order required for programming the password. also, when the password is undergoing programming, simultaneous read/write operation is disabled. read operations to any memory location returns the programming status. once programming is complete, the user must issue a read/reset command to return the device to normal operation. once th e password is written and verified, the password mode locking bit must be set in order to prevent verification. the pass- word program command is only capable of programming ?0?s. programming a ?1? after a cell is programmed as a ?0? results in a time-out by the embedded program algorithm? with the cell remaining as a ?0?. the password is all f?s when shipped from the factory. all 64-bit password combinations are valid as a password. password programming is permitted if the secsi sector is enabled. password verify command the password verify command is used to verify the password. the password is verifiable only when the password mode locking bit is not programmed. if the password mode locking bit is programmed and the user attempts to verify the password, the device always drives all f?s onto the dq data bus. the password verify command is permitted if the secsi sector is enabled. also, simultaneous read/write operation is disabled when the password verify com- mand is executed. only the password is returned regardless of the bank address. the lower two address bits (a0:a-1) are valid during the password verify. writing the read/reset command returns the device back to normal operation.
54 s29cd016g s29cd016_00_a4 november 5, 2004 advance information password protection mode locking bit program command the password protection mode locking bit program command programs the password protection mode locking bit, which prevents further verifies or updates to the password. once programmed, the password protection mode locking bit cannot be erased! if the password protection mode locking bit is verified as pro- gram without margin, the password protection mode locking bit program command can be executed to improve the program margin. once the password protection mode locking bit is programmed, the persistent sector protection locking bit program circuitry is disabled, thereby forcing the device to remain in the password protection mode. exiting the mode locking bit program command is accomplished by writing the read/reset command. the password protection mode locking bit program command is permitted if the secsi sector is enabled. persistent sector protection mode locking bit program command the persistent sector protection mode locking bit program command programs the persistent sector protection mode locking bit, which prevents the password mode locking bit from ever being programmed. if the persistent sector protec- tion mode locking bit is verified as programmed without margin, the persistent sector protection mode locking bit program command should be reissued to im- prove program margin. by disabling the program circuitry of the password mode locking bit, the device is forced to remain in the persistent sector protection mode of operation, once this bit is set. exiting the persistent protection mode locking bit program command is accomplished by writing the read/reset command. the persistent sector protection mode locking bit program command is permitted if the secsi sector is enabled. secsi sector protection bit program command the secsi sector protection bit program command programs the secsi sector protection bit, which prevents the secsi sector memory from being cleared. if the secsi sector protection bit is verified as programmed without margin, the secsi sector protection bit program command should be reissued to improve program margin. exiting the v cc -level secsi sector protection bit program command is accomplished by writing the read/reset command. the secsi sector protection bit program command is permitted if the secsi sector is enabled. ppb lock bit set command the ppb lock bit set command is used to set the ppb lock bit if it is cleared either at reset or if the password unlock command was successfully executed. there is no ppb lock bit clear command. once the ppb lock bit is set, it cannot be cleared unless the device is taken through a pow er-on clear or the password unlock com- mand is executed. upon setting the ppb lock bit, the ppbs are latched into the dybs. if the password mode locking bit is set, the ppb lock bit status is reflected as set, even after a power-on reset cycl e. exiting the ppb lock bit set command is accomplished by writing the read/reset command. the ppb lock bit set command is permitted if the secsi sector is enabled.
november 5, 2004 s29cd016_00_a4 s29cd016g 55 advance information dyb write command the dyb write command is used to set or clear a dyb for a given sector. the high order address bits (a18?a11) are issued at the same time as the code 01h or 00h on dq7-dq0. all other dq data bus pins are ignored during the data write cycle. the dybs are modifiable at any time, regardless of the state of the ppb or ppb lock bit. the dybs are cleared at power-up or hardware reset.exiting the dyb write command is accomplished by writing the read/reset command. the dyb write command is permitted if the secsi sector is enabled. password unlock command the password unlock command is used to clear the ppb lock bit so that the ppbs can be unlocked for modifi cation, thereby allowing the ppbs to become accessible for modification. the exact password must be entered in order for the unlocking function to occur. this command cannot be issued any faster than 2 s at a time to prevent a hacker from running through the all 64-bit combinations in an at- tempt to correctly match a password. if the command is issued before the 2 s execution window for each portion of the unlock, the command is ignored. the password unlock function is accomplished by writing password unlock com- mand and data to the device to perform the clearing of the ppb lock bit. the password is 64 bits long, so the user must write the password unlock command 2 times for a x32 bit data bus. a0 is us ed to determine whether the 32 bit data quantity is used to match the upper 32 bits or lower 32 bits. writing the password unlock command is address order specific. in other words, for the x32 data bus configuration, the lower 32 bits of the password are written first and then the upper 32 bits of the password are written. writing out of sequence results in the password unlock not returning a match with the password and the ppb lock bit remains set. once the password unlock command is entered, the ry/by# pin goes low indi- cating that the device is busy. also, reading the small bank (25% bank) results in the dq6 pin toggling, indicating that the password unlock function is in progress. reading the large bank (75% bank) returns actual array data. approx- imately 1usec is required for each portion of the unlock. once the first portion of the password unlock completes (ry/by# is not driven and dq6 does not toggle when read), the password unlock command is issued again, only this time with the next part of the password. the second password unlock command is the final command before the ppb lock bit is cleared (assuming a valid password). as with the first password unlock command, the ry/by# signal goes low and reading the device results in the dq6 pin toggling on successive read operations until complete. it is the responsibility of the microprocessor to keep track of the num- ber of password unlock commands (2 for x32 bus), the order, and when to read the ppb lock bit to confirm successful password unlock the password unlock command is permitted if the secsi sector is enabled. ppb program command the ppb program command is used to program, or set, a given ppb. each ppb is individually programmed (but is bulk eras ed with the other ppbs). the specific sector address (a18?a11) are written at the same time as the program command 60h with a6 = 0. if the ppb lock bit is set and the corresponding ppb is set for the sector, the ppb program command does not execute and the command times out without programming the ppb.
56 s29cd016g s29cd016_00_a4 november 5, 2004 advance information the host system must determine whether a ppb was fully programmed by noting the status of dq0 in the sixth cycle of the ppb program command. if dq0 = 0, the entire six-cycle ppb program command sequence must be reissued until dq0 = 1. all ppb erase command the all ppb erase command is used to erase all ppbs in bulk. there is no means for individually erasing a specific ppb. un like the ppb program, no specific sector address is required. however, when the ppb erase command is written (60h) and a6 = 1, all sector ppbs are erased in parallel. if the ppb lock bit is set the all ppb erase command does not execute and the command times out without eras- ing the ppbs. the host system must determine whether all ppb was fully erased by noting the status of dq0 in the sixth cycle of the all ppb erase command. if dq0 = 1, the entire six-cycle all ppb erase command sequence must be reissued until dq0 = 1. it is the responsibility of the user to preprogram all ppbs prior to issuing the all ppb erase command. if the user attempts to erase a cleared ppb, over-erasure may occur making it difficult to program the ppb at a later time. also note that the total number of ppb program/erase cycles is limited to 100 cycles. cycling the ppbs beyond 100 cycles is not guaranteed. the all ppb erase command is permitted if the secsi sector is enabled. dyb writ e the dyb write command is used for setting the dyb, which is a volatile bit that is cleared at reset. there is one dyb per sector. if the ppb is set, the sector is protected regardless of the value of the dyb. if the ppb is cleared, setting the dyb to a 1 protects the sector from programs or erases. since this is a volatile bit, removing power or resetting the device clears the dybs. the bank address is latched when the command is written. the dyb write command is permitted if the secsi sector is enabled. ppb lock bit set the ppb lock bit set command is used for setting the dyb, which is a volatile bit that is cleared at reset. there is one dyb per sector. if the ppb is set, the sector is protected regardless of the value of th e dyb. if the ppb is cleared, setting the dyb to a 1 protects the sector from programs or erases. since this is a volatile bit, removing power or resetting the device clears the dybs. the bank address is latched when the command is written. the ppb lock command is permitted if the secsi sector is enabled. dyb st atus the programming of the dyb for a given sector can be verified by writing a dyb status verify command to the device. ppb status the programming of the ppb for a given se ctor can be verified by writing a ppb status verify command to the device. ppb lock bit status the programming of the ppb lock bit for a given sector can be verified by writing a ppb lock bit status verify command to the device.
november 5, 2004 s29cd016_00_a4 s29cd016g 57 advance information non-volatile protection bit program and erase flow the device uses a standard command se quence for programming or erasing the secsi sector protection, password locking, persistent sector protection mode locking, or persistent protection bits. unlike devices that have the single high voltage sector unprotect/protect feature, the device has the standard two-cycle unlock followed by 60h, which places the device into non-volatile bit program or erase mode. once the mode is entered, the specific non-volatile bit status is read on dq0. 1 shows a typical flow for programming the non-volatile bit and 2 shows a typical flow for erasing the non-volatile bits. the secsi sector protection, pass- word locking, persistent sector protection mode locking bits are not erasable after they are programmed. however, the ppbs are both erasable and program- mable (depending upon device security). unlike single high voltage sector protect/unprotect, the a6 pin no longer func- tions as the program/erase selector nor the program/erase margin enable. instead, this function is accomplished by issuing the specific command for either program (68h) or erase (60h). in asynchronous mode, the dq6 toggle bit indicates whether the program or erase sequence is active. (in synchronous mode, adv# indicates the status.) if the dq6 toggle bit toggles with either oe# or ce#, the non-volatile bit program or erase operation is in progress. when dq6 stops toggling, the value of the non- volatile bit is available on dq0.
58 s29cd016g s29cd016_00_a4 november 5, 2004 advance information table 19. memory array command definitions (x32 mode) command (notes) cycles bus cycles (notes 1?4) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (5) 1 ra rd reset (6) 1 xxx f0 autoselect (7) manufacturer id 4 555 aa 2aa 55 555 90 ba+x00 01 device id (11) 6 555 aa 2aa 55 555 90 ba+x01 7e ba+x0e 36 ba+x0f 00/ 01 program 4 555 aa 2aa 55 555 a0 pa pd chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 program/erase suspend (12) 1 ba b0 program/erase resume (13) 1 ba 30 cfi query (14, 15) 1 55 98 accelerated program (16) 2 xx a0 pa pd configuration register verify (15) 3 555 aa 2aa 55 ba+555 c6 ba+xx rd configuration register write (17) 4 555 aa 2aa 55 555 d0 xx wd unlock bypass entry (18) 3 555 aa 2aa 55 555 20 unlock bypass program (18) 2 xx a0 pa pd unlock bypass erase (18) 2 xx 80 xx 10 unlock bypass cfi (14, 18) 1 xx 98 unlock bypass reset (18) 2 xx 90 xx 00 legend: ba = address of the bank that is being switched to autoselect mode, is in bypass mode, or is being er ased. determined by a18 and a17, see tables 11 and 12 for more detail. pa = program address (a18:a0). addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = program data (dq31:dq0) written to location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. ra = read address (a18:a0). rd = read data (dq31:dq0) from location ra. sa = sector address (a18:a11) for verifying (in autoselect mode), erasing, or applying security commands. wd = write data. see ?configuration register? definition for specific write data. data latched on rising edge of we#. x = don?t care notes: 1. see table 1 on page 14 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells in table denote read cycles. all other cycles are write operations. 4. during unlock cycles, (lower address bits are 555 or 2aah as shown in table) address bits higher than a11 (except where ba is required) and data bits higher than dq7 are don?t cares. 5. no unlock or command cycles required when bank is reading array data. 6. the reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in erase suspend) when a bank is in the autoselect mode, or if dq5 goes high (while the bank is providing status information). 7. the fourth cycle of the autoselect command sequence is a read cycle. the system must provide the bank address to obtain the manufacturer id or device id information. see the ?autoselect command? on page 44 section for more information. 8. this command cannot be executed until the unlock bypass command must be executed before writing this command sequence. the unlock bypass reset command must be executed to return to normal operation. 9. this command is ignored during any embedded program, erase or suspended operation. 10. valid read operations include asynchronous and burst read mode operations. 11. the device id must be read across the fourth, fifth, and sixth cycles. 00h in the sixth cycle indicates ordering option 00, 01h indicates ordering option 01. 12. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the program/erase suspend mode. the program/erase suspend command is valid only during a sector erase operation, and requires the bank address. 13. the program/erase resume command is valid only during the erase suspend mode, and requires the bank address. 14. command is valid when device is ready to read array data or when device is in autoselect mode. 15. asynchronous read operations. 16. acc must be at v id during the entire operation of this command. 17. command is ignored during any embedded program, embedded erase, or suspend operation. 18. the unlock bypass entry command is required prior to any unlock bypass operation. the unlock bypass reset command is required to return to the read mode.
november 5, 2004 s29cd016_00_a4 s29cd016g 59 advance information table 20. sector protection command definitions (x32 mode) command (notes) cycles bus cycles (notes 1-4) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data reset 1 xxx f0 secsi sector entry 3 555 aa 2aa 55 555 88 secsi sector exit 4 555 aa 2aa 55 555 90 xx 00 secsi protection bit program (5, 6) 6 555 aa 2aa 55 555 60 ow 68 ow 48 ow rd(0) secsi protection bit status 6 555 aa 2aa 55 555 60 ow rd(0) password program (5, 7, 8) 4 555 aa 2aa 55 555 38 pwa[0-1] pwd[0-1] password verify 4 555 aa 2aa 55 555 c8 pwa[0-1] pwd[0-1] password unlock (7, 8) 5 555 aa 2aa 55 555 28 pwa[0-1] pwd[0-1] ppb program (5, 6) 6 555 aa 2aa 55 555 60 sg+wp 68 sg+wp 48 sg+wp rd(0) all ppb erase (5, 9, 10) 6 555 aa 2aa 55 555 60 wp 60 wp 40 wp rd(0) ppb status (11, 12) 4 555 aa 2aa 55 sg+555 90 sa+x02 00/01 ppb lock bit set 3 555 aa 2aa 55 555 78 ppb lock bit status 4 555 aa 2aa 55 555 58 sa rd(1) dyb write (7) 4 555 aa 2aa 55 555 48 sa x1 dyb erase (7) 4 555 aa 2aa 55 555 48 sa x0 dyb status (12) 4 555 aa 2aa 55 sa+555 58 sa rd(0) ppmlb program (5,6) 6 555 aa 2aa 55 555 60 pl 68 pl 48 pl rd(0) ppmlb status (5) 6 555 aa 2aa 55 555 60 pl rd(0) spmlb program (5, 6) 6 555 aa 2aa 55 555 60 sl 68 sl 48 sl rd(0) spmlb status (5) 6 555 aa 2aa 55 555 60 sl rd(0) legend: dyb = dynamic protection bit ow = address (a5?a0) is (011x10). ppb = persistent protection bit pwa = password address. a0 selects between the low and high 32-bit portions of the 64-bit password pwd = password data. must be written over two cycles. pl = password protection mode lock address (a5?a0) is (001x10) rd(0) = read data dq0 protection indicator bit. if protected, dq0= 1, if unprotected, dq0 = 0. rd(1) = read data dq1 protection indicator bit. if protected, dq1 = 1, if unprotected, dq1 = 0. sa = sector address where security command applies. address bits a18:a11 uniquely select any sector. sg = sector group address ba = bank address sl = persistent protection mode lock address (a5?a0) is (010x10) wp = ppb address (a5?a0) is (111010) x = don?t care ppmlb = password protection mode locking bit spmlb = persistent protection mode locking bit notes: 1. see table 1 on page 14 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells in table denote read cycles. all other cycles are write operations. 4. during unlock cycles, (lower address bits are 555 or 2aah as shown in table) address bits higher than a11 (except where ba is required) and data bits higher than dq7 are don?t cares. 5. the reset command returns the device to reading the array. 6. the fourth cycle programs the addressed locking bit. the fifth and sixth cycles are used to validate whether the bit was fully programmed. if dq0 (in the sixth cycle) reads 0, the program command must be issued and verified again. 7. data is latched on the rising edge of we#. 8. the entire four bus-cycle sequence must be entered for each portion of the password. 9. the fourth cycle erases all ppbs. the fifth and sixth cycles are used to validate whether the bits were fully erased. if dq0 (in the sixth cycle) reads 1, the erase command must be issued and verified again. 10. before issuing the erase command, all ppbs should be programmed in order to prevent over-erasure of ppbs. 11. in the fourth cycle, 00h indicates ppb set; 01h indicates ppb not set. 12. the status of additional ppbs and dybs may be read (following the fourth cycle) without reissuing the entire command sequence.
60 s29cd016g s29cd016_00_a4 november 5, 2004 advance information write operation status the device provides several bits to determine the status of a write operation: dq2, dq3, dq5, dq6, dq7, and ry/by#. table 21 on page 65 and the following subsections describe the functions of th ese bits. dq7, ry/by#, and dq6 each offer a method for determin ing whether a program or erase operation is complete or in progress. these three bits are discussed first. dq7: data# polling the device features a data# polling flag as a method to indicate to the host sys- tem whether the embedded algorithms are in progress or are complete. during the embedded program algorithm an attempt to read the bank in which program- ming was initiated produces the complement of the data last written to dq7. upon completion of the embedded program algorithm, an attempt to read the de- vice produces the true last data written to dq7. note that data# polling returns invalid data for the address being programmed or erased. for example, the data read for an address programmed as 0000 0000 1000 0000b returns xxxx xxxx 0xxx xxxxb during an embedded program operation. once the embedded program algorithm is complete, the true data is read back on dq7. note that at the instant when dq7 switches to true data, the other bits may not yet be true. however, they will all be true data on the next read from the device. please note that data# polling ma y give misleading status when an at- tempt is made to write to a protected sector. for chip erase, the data# polling flag is valid after the rising edge of the sixth we# pulse in the six write pulse sequence. for sector erase, the data# polling is valid after the last rising edge of the sector erase we# pulse. data# polling must be performed at sector addresses within any of the sectors being erased and not a sector that is a protected sector. otherwise, the status may not be valid. dq7 = 0 during an embedded erase algorithm (chip erase or sector erase operation) but returns a ?1? after the operation comp letes because it drops back into read mode. in asynchronous mode, just prior to th e completion of the embedded algorithm operations, dq7 may change asynchronously while oe# is asserted low. (in syn- chronous mode, adv# exhibits this behavior.) the status information may be invalid during the instance of transition from status information to array (mem- ory) data. an extra validity check is therefore specified in the data polling algorithm. the valid array data on dq31?dq0 is available for reading on the next successive read attempt. the data# polling feature is only active during the embedded programming al- gorithm, embedded erase algorithm, erase suspend, erase suspend-program mode, or sector erase time-out. if the user attempts to write to a protected sector, data# polling is activated for about 1 s: the device then returns to read mode, with the data from the pro- tected sector unchanged. if the user atte mpts to erase a protected sector, toggle bit (dq6) is activated for about 150 s; the device then returns to read mode, without having erased the protected sector. table 21 on page 65 shows the outputs for data# polling on dq7. figure 6, on page 61 shows the data# polling algorithm. figure 24, on page 80 shows the timing diagram for synchronous status dq7 data polling.
november 5, 2004 s29cd016_00_a4 s29cd016g 61 advance information dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start notes: 1. va = valid address for programming. during a sector erase operation, a valid address is an address within any sector selected for erasure. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5. figure 6. data# polling algorithm
62 s29cd016g s29cd016_00_a4 november 5, 2004 advance information ry/by#: ready/busy# the device provides a ry/by# open drain output pin as a way to indicate to the host system that the embedded algorith ms are either in progress or are com- pleted. if the output is low, the device is busy with either a program, erase, or reset operation. if the output is floating , the device is ready to accept any read/ write or erase operation. when the ry/by# pin is low, the device does not accept any additional program or erase commands with the exception of the erase sus- pend command. if the device enters erase suspend mode, the ry/by# output is floating. for programming, the ry/by# is valid (ry/by# = 0) after the rising edge of the fourth we# pulse in the four write pulse sequence. for chip erase, the ry/ by# is valid after the rising edge of the sixth we# pulse in the six write pulse sequence. for sector erase, the ry/by# is also valid after the rising edge of the sixth we# pulse. if reset# is asserted during a program or erase operation, the ry/by# pin re- mains a ?0? (busy) until the internal res et operation is complete, which requires a time of t ready (during embedded algorithms). th e system can thus monitor ry/ by# to determine whether the reset operatio n is complete. if reset# is asserted when a program or erase operation is not executing (ry/by# pin is ?floating?), the reset operation is completed in a time of t ready (not during embedded algo- rithms). the system can read data t rh after the reset# pin returns to v ih . since the ry/by# pin is an open-drain output, several ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . an external pull-up resistor is required to take ry/by# to a v ih level since the output is an open drain. table 21 on page 65 shows the outputs for ry/by#. figure 16, on page 73 , figure 19, on page 75 , figure 21, on page 78 and figure 23, on page 79 shows ry/by# for read, reset, program, and erase operations, respectively. dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or completed, or whether the device entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operation, two immediately consecutive read cycles to any address cause dq6 to toggle. when the operation is complete, dq6 stops toggling. for asynchronous mode, either oe# or ce# can be used to control the read cycles. for synchronous mode, the rising edge of adv# is used or the rising edge of clock while adv# is low. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algo- rithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to determine whether a sector is ac- tively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device en- ters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alter- natively, the system can use dq7 (see the subsection on ?dq7: data# polling? on page 60 ).
november 5, 2004 s29cd016_00_a4 s29cd016g 63 advance information if a program address falls within a protected sector, dq6 toggles for approxi- mately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. table 21 on page 65 shows the outputs for toggle bit i on dq6. figure 7, on page 64 shows the toggle bit algorithm in flowchart form, and the section ?read- ing toggle bits dq6/dq2? on page 63 explains the algorithm. figure 25, on page 80 shows the toggle bit timing diagrams. figure 25, on page 80 shows the differences between dq2 and dq6 in graphical form. see also the subsection on ?dq2: toggle bit ii? . figure 25, on page 80 shows the timing diagram for syn- chronous toggle bit status. dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system performs two immediately consecutive reads at addresses within those sectors that were selected for erasure. (for asynchronous mode, either oe# or ce# can be used to control the read cycles. for synchronous mode, adv# is used.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both stat us bits are required for sector and mode information. refer to table 21 on page 65 to compare outputs for dq2 and dq6. figure 7, on page 64 shows the toggle bit algorithm in flowchart form, and the section ?reading toggle bits dq6/dq2? on page 63 explains the algorithm. see also the ?dq6: toggle bit i? on page 62 subsection. figure 25, on page 80 shows the toggle bit timing diagram. figure 26, on page 81 shows the differences be- tween dq2 and dq6 in graphical form. figure 27, on page 81 shows the timing diagram for synchronous dq2 toggle bit status. reading toggle bits dq6/dq2 refer to figure 26, on page 81 for the following discussion. whenever the sys- tem initially begins reading toggle bit st atus, it must perform two immediately consecutive reads of dq7?dq0 to determin e whether a toggle bit is toggling. typ- ically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the tog- gle bit with the first. if the toggle bit is not toggling, the device completed the program or erase operation. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initial two immedi ately consecutive read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device successfully completed the program or erase operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data.
64 s29cd016g s29cd016_00_a4 november 5, 2004 advance information the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as de- scribed in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algo- rithm when it returns to determine th e status of the operation (top of figure 7 ). start no yes yes dq5 = 1? no yes dq6 = toggle? no read byte (dq0-dq7) address = va dq6 = toggle? read byte twice (dq 0-dq7) adrdess = va read byte (dq0-dq7) address = va fail pass notes: 1. read toggle bit with two immediately consecutive reads to determine whether or not it is toggling. see text. 2. recheck toggle bit because it may stop toggling as dq5 changes to ?1?. see text. figure 7. toggle bit algorithm (note 1) (notes 1, 2)
november 5, 2004 s29cd016_00_a4 s29cd016g 65 advance information dq5: exceeded timing limits dq5 indicates whether the program or erase time exceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1.? this is a failure condition that indicates the program or erase cycle was not successfully completed. the dq5 failure condition may appear if the system tries to program a ?1? to a location that is previously programmed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the opera- tion, and when the operation exceeds the timing limits, dq5 produces a ?1.? under both these conditions, the system must issue the reset command to return the device to reading array data. dq3: sector erase timer after writing a sector erase command se quence, the system may read dq3 to de- termine whether or not an er ase operation started. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for era- sure, the entire time-out also applie s after each additional sector erase command. when the time-out is complete, dq3 switches from ?0? to ?1.? the system may ignore dq3 if the system can guarantee that the time between ad- ditional sector erase commands is always less than 50 s. see also ?sector erase command? on page 48 . after the sector erase command sequence is written, the system should read the status on dq7 (data# polling) or dq6 (to ggle bit i) to ensure the device accepted the command sequence, and then read dq3. if dq3 is ?1?, the internally con- trolled erase cycle started; all further commands (other than erase suspend) are ignored until the erase operation is comple te. if dq3 is ?0?, the device accepts additional sector erase commands. to ensure the command was accepted, the system software should check the status of dq3 prior to and following each sub- sequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. table 21 on page 65 shows the outputs for dq3. ta b l e 2 1 . write operation status notes: 1. dq5 switches to ?1? when an embedded program or embedded erase operation exceeds the maximum timing limits. see ?dq5: exceeded timing limits? on page 65 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. operation dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle 0 erase suspend mode reading within erase suspended sector 1 no toggle 0 n/a toggle 1 reading within non-erase suspended sector data data data data data 1 erase-suspend-program dq7# toggle 0 n/a n/a 0
66 s29cd016g s29cd016_00_a4 november 5, 2004 advance information absolute maximum ratings storage temperature, plastic packages . . . . . . . . . . . . . . . . ?65c to +150c ambient temperature with power applied . . . . . . . . . . . . . . ?65c to +145c v cc , v io (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to + 3.0 v acc, a9 , oe# , and reset# (note 2) . . . . . . . . . . . . . . . . . ?0.5 v to +13.0 v address, data, control signals (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to 3.60 v all other pins (note 1) . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +3.60 v output short circuit current (note 3). . . . . . . . . . . . . . . . . . . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, input at i/o pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. see 6. maximum dc voltage on output and i/o pins is 3.6 v. during voltage transitions output pins may overshoot to v cc + 2.0 v for periods up to 20 ns. see figure 6. 2. minimum dc input voltage on pins acc, a9, oe#, and reset# is -0.5 v. during voltage transitions, a9, oe#, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 5. maximum dc input voltage on pin a9 and oe# is +13.0 v which may overshoot to 14.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. 4. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. expo sure of the device to absolute maximum rating conditions for extended periods may affect device reliability. operating ranges industrial (i) devices ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . ?40c to +85c extended (e) devices ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . ?40c to +125c v cc supply voltages v cc for regulated voltage range . . . . . . . . . . . . . . . . . . . . . . . 2.5 v to 2.75 v v io supply voltages v io . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.65 v to 2.75 v operating ranges define those limits between which the functionality of the device is guaranteed. figure 8. maximum negative overshoot waveform figure 9. maximum positive overshoot waveform 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v
november 5, 2004 s29cd016_00_a4 s29cd016g 67 advance information dc characteristics notes: 1. the i cc current listed includes both the dc operating current and the frequency dependent component. 2. i cc active while embedded erase or embedded program is in progress. 3. not 100% tested. 4. maximum i cc specifications are tested with v cc = v ccmax . 5. current maximum was increased significantly from data sheet revision b+4, dated april 8, 2003. 6. pull-up 6resistor is required. ta b l e 2 2 . cmos compatible parameter description test conditions min typ max unit i li input load current v in = v ss to v io , v io = v io max 1.0 a i liwp wp# input load current v in = v ss to v io , v io = v io max ?25 a i lit a9, acc input load current v cc = v ccmax ; a9 = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i ccb v cc active burst read current (note 1) ce# = v il , oe# = v il 56 mhz 8 double-word 70 90 ma 66 mhz i cc1 v cc active asynchronous read current (note 1) ce# = v il , oe# = v il 1 mhz 10 ma i cc3 v cc active program current (notes 2, 4) ce# = v il , oe# = v ih , acc = v ih 40 50 ma i cc4 v cc active erase current (notes 2, 4) ce# = v il , oe# = v ih , acc = v ih 20 50 ma i cc5 v cc standby current (cmos) (note 5) v cc = v cc max , ce# = v cc 0.3 v 60 a i cc6 v cc active current (read while write) ce# = v il , oe# = v il 30 90 ma i cc7 v cc reset current (note 5) reset# = v il 60 a i cc8 automatic sleep mode current (note 5) v ih = v cc 0.3 v, v il = v ss 0.3 v 60 a i acc v acc acceleration current acc = v hh 20 ma v il input low voltage ?0.5 0.3 x v io v v ih input high voltage 0.7 x v io 3.6 v v ilclk clk input low voltage ?0.2 0.3 x v io v v ihclk clk input high voltage 0.7 x v cc 2.75 v v id voltage for autoselect v cc = 2.5 v 11.5 12.5 v v ol output low voltage i ol = 4.0 ma, v cc = v cc min 0.4 v i olrb ry/by#, output low current (note 6) v ol = 0.4 v 1 ma v hh accelerated (acc pin) high voltage v cc = v cc min 11.5 12.5 v v oh output high voltage i oh = ?100 a, v cc = v cc min v io ?0.4 v v lko low v cc lock-out voltage (note 3) 1.6 2.0 v
68 s29cd016g s29cd016_00_a4 november 5, 2004 advance information dc characteristics (continued) zero power flash note: addresses are switching at 1 mhz figure 10. i cc1 current vs. time (showing active and automatic sleep currents) 5 4 3 2 1 0 0 500 1000 1500 2000 2500 3000 3500 4000 supply current in ma time in ns 20 16 4 0 12345 frequency in mhz supply current in ma note: t = -40 c figure 11. typical i cc1 vs. frequency 2.7 v 8 12
november 5, 2004 s29cd016_00_a4 s29cd016g 69 advance information test conditions key to switching waveforms switching waveforms table 23. test specifications test condition 40 mhz (oj), 56 mhz (om) 66 mhz (op) unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 100 pf input rise and fall times 5 ns input pulse levels 0.0 v ? v io v input timing measurement reference levels v io /2 v output timing measurement reference levels v io /2 v figure 12. test setup n ote: diodes are in3064 or equivalent c l device under te st waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) v io v ss v io /2 v io /2 output measurement level in figure 13. input waveforms and measurement levels
70 s29cd016g s29cd016_00_a4 november 5, 2004 advance information ac characteristics v cc and v io power-up figure 14. v cc and v io power-up diagram parameter description test setup speed unit t vcs v cc setup time min 50 s t vios v io setup time min 50 s t rsth reset# low hold time min 50 s v cc v iop reset# t vcs t rsth t vios
november 5, 2004 s29cd016_00_a4 s29cd016g 71 advance information ac characteristics ta b l e 2 4 . asynchronous read operations notes: 1. not 100% tested. 2. see figure 12, on page 69 and table 23 on page 69 for test specifications figure 15. conventional read operations timings parameter description test setup speed options unit jedec std. 66 mhz (op) 55 mhz (om) 40 mhz (oj) t avav t rc read cycle time (note 1) max 54 64 67 ns t avqv t acc address to output delay ce# = v il oe# = v il max 54 64 67 ns t elqv t ce chip enable to output delay oe# = v il max 58 69 71 ns t glqv t oe output enable to output delay max 20 20 28 ns t ehqz t df chip enable to output high z (note 1) max 10 ns t ghqz t df output enable to output high z (note 1) min 2 ns max 10 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first (note 1) min 2 ns t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t oe 0 v ry/by# reset# t df t oh
72 s29cd016g s29cd016_00_a4 november 5, 2004 advance information ac characteristics ta b l e 2 5 . burst mode read parameter description speed options unit jedec std. 66 mhz (0p) 56 mhz (0m) 40 mhz (0j) t bacc burst access time valid clock to output delay max 9 fbga 9.5 pqfp 10 fbga 10 pqfp 17 ns t advcs adv# setup time to rising edge of clk min 6 ns t advch adv# hold time from rising edge of clk min 1.5 1.5 1.5 ns t advp adv# pulse width min 13 15 22 ns t dvch valid data hold from clk min 2 3 3 ns t dind clk to valid ind/wait# max 9 fbga 9.5 pqfp 10 fbga 10 pqfp 17 ns t indh ind/wait# hold from clk min 2 3 3 ns t iacc clk to valid data out, initial burst access max 54.45 63.55 67 ns t clk clk period min 15.15 17.85 25 ns max 60 3 3 t cr clk rise time max ns t cf clk fall time max ns t ch clk high time min 2.5 2.5 3 ns t cl clk low time min 2.5 2.5 3 ns t ds data setup to we# rising edge min 18 ns t dh data hold from we# rising edge min 2 ns t as address setup to falling edge of we# min 0 ns t ah address hold from falling edge of we# min 22 23 24 ns t cs ce# setup time min 4 ns t ch ce# hold time min 3 ns t acs address setup time to clk min 6 ns t ach address hold time from adv# rising edge of clk while adv# is low min 5 ns t oe output enable to output valid max 20 20 28 ns t df t oez output enable to output high z min 2 3 3 ns max 10 15 17 t ehqz t cez chip enable to output high z max 10 15 17 ns t ces ce# setup time to clock min 6 ns
november 5, 2004 s29cd016_00_a4 s29cd016g 73 advance information ac characteristics figure 16. burst mode read (x32 mode) da da + 2 da + 3 da + 31 oe#* data addresses aa ind# adv# clk ce# t ces t acs t advcs t advch t ach t oe t bacc t bdh t oez t cez t iacc da + 1
74 s29cd016g s29cd016_00_a4 november 5, 2004 advance information ac characteristics figure 17. asynchronous command write timing note: all commands have the same number of cycles in both asynchronous and synchronous modes, including the read/reset command. only a single array access occurs after the f0h command is entered. all subsequent accesses are burst mode when the burst mode option is enabled in the configuration register. figure 18. synchronous command write/read timing note: all commands have the same number of cycles in both asynchronous and synchronous modes, including the read/reset command. only a single array access occurs after the f0h command is entered. all subsequent accesses are burst mode when the burst mode option is enabled in the configuration register. adv# ce# valid data addresses data we# oe# ind/wait# clk stable address t cs t ch t as t ah t oeh t ds t dh t wph t wc t as clk adv# data in addresses data oe# data out we# ind/wait# ce# valid address t ds t wp t ces t advp t advcs t oe t acs t acs t df t ehqz t dh t wadvh t advch t wadvh2 t ach t wc t ap t wcks valid
november 5, 2004 s29cd016_00_a4 s29cd016g 75 advance information ac characteristics note: not 100% tested. ta b l e 2 6 . hardware reset (reset#) parameter description all speed options jedec std. test setup unit t ready reset# pin low (during embedded algorithms) to read or write (see note) max 11 s t ready reset# pin low (not during embedded algorithms) to read or write (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset# high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 s reset# ry/by# ry/by# t rp t ready reset timing to bank not executing embedded algorithm t ready ce#, oe# t rh ce#, oe# reset timing to bank executing embedded algorithm reset# t rp t rb figure 19. reset# timings
76 s29cd016g s29cd016_00_a4 november 5, 2004 advance information ac characteristics figure 20. wp# timing program/erase command wp# data valid wp# t ch t ds t dh we# ry/by# t wpws t wprh t wp
november 5, 2004 s29cd016_00_a4 s29cd016g 77 advance information ac characteristics erase/program operations notes: 1. not 100% tested. 2. see table 29 on page 85 for more information. table 27. erase/program operations parameter all speed options jedec std. description unit t avav t wc write cycle time (note 1) min 60 ns t avwl t as address setup time min 0 ns t wlax t ah address hold time min 25 ns t dvwh t ds data setup to we# rising edge min 15 ns t whdx t dh data hold from we# rising edge min 2 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 2 ns t wlwh t wp we# width min 25 ns t whwl t wph write pulse width high min 30 ns t wadvh1 we# falling edge after adv# falling edge min 0 ns t wadvh2 we# rising edge after adv# rising edge min 10 ns t wcks we# rising edge setup to clk rising edge min 5 ns t whwh1 t whwh1 programming operation (note 2) double-word typ 18 s t whwh2 t whwh2 sector erase operation (note 2) typ 1.0 sec. t vcs v cc setup time (note 1) min 50 s t rb recovery time from ry/by# min 0 ns t busy ry/by# delay after we# rising edge max 90 ns t wpws wp# setup to we# rising edge with command min 20 ns t wprh wp# hold after ry/by# rising edge max 2 ns
78 s29cd016g s29cd016_00_a4 november 5, 2004 advance information ac characteristics notes: pa = program address, pd = program data, d out is the true data at the program address. figure 21. program operation timings oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs statu d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa
november 5, 2004 s29cd016_00_a4 s29cd016g 79 advance information ac characteristics note: sa = sector address (for sector erase), va = valid address for reading status data (see table 21 on page 65 ). figure 22. chip/sector erase operation timings figure 23. back-to-back cycle timings oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase t ds t vcs t cs t dh t ch t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy 55h 30h in progress complete oe# ce# we# addresses t oh data valid in valid in valid pa valid ra t wc t wph t ah t wp t ds t dh t rc t ce valid out t oe t acc t oeh t ghwl t df valid in ce# controlled write cycles we# controlled write cycle valid pa valid pa t cp t cph t wc t wc read cycle t sr/w t wph
80 s29cd016g s29cd016_00_a4 november 5, 2004 advance information ac characteristics we# ce# oe# high z t oe high z dq7 data ry/by# t busy complement true addresses va t oeh t ce t ch t oh t df va va status data complement status data true valid data valid data t acc t rc t wc note: va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. figure 24. data# polling timings (during embedded algorithms) we# ce# oe# high z t oe dq6/dq2 ry/by# t busy addresses va t oeh t ce t ch t oh t df va va t acc t rc valid data valid status valid status (first read) (second read) (stops toggling) valid status va note: va = valid address; not required for dq6. illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. figure 25. toggle bit timings (during embedded algorithms)
november 5, 2004 s29cd016_00_a4 s29cd016g 81 advance information ac characteristics note: the system may use ce# or oe# to toggle dq2 and dq6. dq2 toggles only when read at an address within an erase-suspended sector. figure 26. dq2 vs. dq6 for erase/erase suspend operations enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing ce# clk avd# addresses oe# data rdy status data status data va va t oe t oe notes: 1. the timings are similar to synchronous read timings and asynchronous data polling timings/toggle bit timing. 2. va = valid address. two read cycles are required to determine status. when the embedded algorithm operation is complete, the toggle bits stops toggling. 3. rdy is active with data (a18 = 0 in the configuration register). when a18 = 1 in the configuration register, rdy is active one clock cycle before data. 4. data polling requires burst access time delay. figure 27. synchronous data po lling timing/toggle bit timings
82 s29cd016g s29cd016_00_a4 november 5, 2004 advance information ac characteristics sector protect: 150 s sector unprot ect: 15 ms 1 s reset# sa, a6, a1, a0 data ce# we# oe# 60h 60h/68h** 40h/48h*** valid* valid* valid* status sector protect/unprotect verify v ih * valid address for sector protect: a[7:0] = 3ah. valid address for sector unprotect: a[7:0] = 3ah. ** command for sector protect is 68h. command for sector unprotect is 60h. *** command for sector protect verify is 48h. command for sector unprotect verify is 40h. figure 28. sector protect/unprotect timing diagram
november 5, 2004 s29cd016_00_a4 s29cd016g 83 advance information ac characteristics ta b l e 2 8 . alternate ce# controlled erase/program operations notes: 1. not 100% tested. 2. see the section for more information. parameter all speed options jedec std. description unit t avav t wc write cycle time (note 1) min 65 ns t avel t as address setup time min 0 ns t elax t ah address hold time min 45 ns t dveh t ds data setup time min 35 ns t ehdx t dh data hold time min 2 ns t oes output enable setup time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t wp we# width min 32 ns t wph write pulse width high min 40 ns t wadvh we# falling edge after min 0 ns t wcks we# rising edge setup to clk rising edge min 5 ns t eleh t cp ce# pulse width min 16 ns t ehel t cph ce# pulse width high min 30 ns t whwsh1 t whwh1 programming operation (note 2) double-word typ 18 s t whwh2 t whwh2 sector erase operation (note 2) typ 1.0 sec.
84 s29cd016g s29cd016_00_a4 november 5, 2004 advance information ac characteristics t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy t wph t wp notes: 1. pa = program address, pd = program data, dq7# = complement of the data written to the device, d out = data written to the device. 2. the figure indicates the last two bus cycles of the command sequence. figure 29. alternate ce# controlled write operation timings
november 5, 2004 s29cd016_00_a4 s29cd016g 85 advance information ta b l e 2 9 . erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 2.5 v v cc , 100,000 cycles. additionally, programming typicals assume checkerboard pattern. 2. under worst case conditions of 145c, v cc = 2.5 v, 1,000,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed. 4. in the pre-programming step of the embedded erase algo rithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execut e the two- or four-bus-cycle sequence for the program command. see table 19 on page 58 and table 20 on page 59 for further information on command definitions. 6. ppbs have a program/erase cycle endurance of 100 cycles. ta b l e 3 0 . pqfp and fortified bga pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. parameter typ (note 1) max (note 2) unit comments sector erase time 1.0 5 s excludes 00h programming prior to erasure (note 4) chip erase time 46 230 s double word program time 18 250 s excludes system level overhead (note 5) accelerated double word program time 8 130 s accelerated chip program time 5 50 s chip program time (note 3) x32 12 120 s parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 7.5 9 pf
86 s29cd016g s29cd016_00_a4 november 5, 2004 advance information physical dimensions prq080?80-lead plastic quad flat package 3213\38.4 c package pqr 080 jedec mo-108(b)cb-1 notes symbol min nom max a -- -- 3.35 a1 0.25 -- -- a2 2.70 2.80 2.90 b 0.30 -- 0.45 see note 4 c 0.15 -- 0.23 d 17.00 17.20 17.40 d1 13.90 14.00 14.10 see note 3 d3 -- 12.0 -- reference e -- 0.80 -- basic, see note 7 e 23.00 23.20 23.40 e1 19.90 20.00 20.10 see note 3 e3 -- 18.40 -- reference aaa --- 0.20 --- ccc 0.10 l 0.73 0.88 1.03 p24 q40 r64 s80 notes: 1. all dimensions and tolerances conform to ansi y14.5m-1982. 2. datum plane -a- is located at the mold parting line and is coincident with the bottom of the lead where the lead exits the plastic body. 3. dimensions "d1" and "e1" do not includ mold protrusion . allowable protrusion is 0.25 mm per side. dimensions "d1" and "e1" include mold mismatch and are determined at datum plane -a- 4. dimension "b" does not include dambar protrusion. 5. controlling dimensions: millimeter. 6. dimensions "d" and "e" are measured from both innermost and outermost points. 7. deviation from lead-tip true position shall be within ?.0076 mm for pitch > 0.5 mm and within ?.04 for pitch < 0.5 mm. 8. lead coplanarity shall be within: (refer to 06-500) 1 - 0.10 mm for devices with lead pitch of 0.65 - 0.80 mm 2 - 0.076 mm for devices with lead pitch of 0.50 mm. coplanarity is measured per specification 06-500. 9. half span (center of package to lead tip) shall be within ?.0085". b c section s-s 6 3 3 6 -b- pin r pin s -a- pin one i.d. d1 d d3 pin q -d- p in p e e1 e3 see note 3 a a1 a2 -c- -a- seating plane 2 e basic see detail x s s detail x 0.25 a c ccc sd s 4 c ab m a a b 0?-7? a 0?min. l gage plane 7? typ. 0.30 ?0.05 r 7? typ. 0.20 min. flat shoulder
november 5, 2004 s29cd016_00_a4 s29cd016g 87 advance information physical dimensions laa080?80-ball fortified ball grid array (13 x 11 mm) 3214\38.12c package laa 080 jedec n/a 13.00 x 11.00 mm note package symbol min nom max a -- -- 1.40 profile height a1 0.40 -- -- standoff a2 0.60 -- -- body thickness d 13.00 bsc. body size e 11.00 bsc. body size d1 9.00 bsc. matrix footprint e1 7.00 bsc. matrix footprint md 10 matrix size d direction me 8 matrix size e direction n 80 ball count b 0.50 0.60 0.70 ball diameter ed 1.00 bsc. ball pitch - d direction ee 1.00 bsc. ball pitch - e direction sd/se 0.50 bsc solder ball placement notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row , sd or se = e/2 8. n/a 9. "+" indicates the theoretical center of depopulated balls. bottom view side view top view 2x 2x c 0.20 c 0.20 6 7 7 a c c 0.10 0.25 m m b c 0.25 0.15 c a b c seating plane j k ed (ink or laser) corner a1 a2 d e 0.50 a1 corner id. 1.00?.5 1.00?.5 a a1 corner a1 nx b sd se ee e1 d1 1 2 3 4 5 6 7 8 a cb d fe g h
88 s29cd016g s29cd016_00_a4 november 5, 2004 advance information revision summary revision a1 (march 22, 2004) performance characteristics burst mode read: changed to 66-mhz. ordering information changed device number/description call out to show the two 16-mbit configurations. table 12 and table 13 corrected which sectors report to which bank. asynchronous read operations table removed the or speed option. revision a2 (may 24, 2004) ?spansion? logo replaces amd in bullet seven, first column. fujitsu mbm29lv and mbm129f added to bullet ten, first column. ultra low power consumption bullet ?capable of...? deleted from first bullet, second column. block diagram reset# moved, ry/by added. simultaneous read/write circuit block diagram ry/by added; bank 1 added; bank 0 added. pin configuration ?a pull-up resistor of 10k...? added to ry/by#. ordering information additional ordering options update d to ?protects sectors 44 and 45?. device number/description bit description altered. simultaneous read/write operation with zero latency table 3 and 4 bank # change. auto select mode table 5: manufacturer id row updated (a3, a2). table 5: dq7 to dq0 column updated. linear burst read operations table 6: ?(x16)? removed from header row. ind/wait# operation in linear mode figure 2 - ?address 2? removed. initial burst access delay control figure 3 - valid address line changed. notes - clock cycles updated.
november 5, 2004 s29cd016_00_a4 s29cd016g 89 advance information configuration register table 9: cr14 reserve bit assigned asd. table 9: speed options changed. table 10: cr14 reserve changed to asd. table12. sector addresses for ordering option 00 bank changed to 0. bank changed to 1. table 13. sector addresses for ordering option 01 bank changed to 0. bank changed to 1. table 16. device geometry definition 0005 = supports x16 and x32 via word#...? removed. unlock bypass command sequence table ?18? replaced with ?19? in text. table 19. memory array command definitions (x32 mode) autoselect (7) - device id (11); fifth/data changed to ?36?. table 20. sector protection command definitions (x32 mode) pbb status (11,12) third/addr changed to ?sg?. ppb lock bit status; third/addr ?ba? removed. dyb status; third/addr changed to ?sa?. absolute maximum ratings address, data... changed to 3.6v. table 22 cmos compatible input high voltage max changed to 3.6. ry/by#, output low current min re- moved, max added (8). table 23. test specifications test conditions changed to oj,om,op. ac characteristics figure 14 updated reset#. table number 24. asynchronous read operations om speed options; output enable to output delay ?20? added. table 26. hardware reset last row deleted. erase/program operations twadvh row added. twcks row added. table 27. alternate ce# controlled erase/program operations twph row added, twadvh row added, twcks row added. physical dimensions latchup characteristics deleted. pin description ?wait# provides data valid feedback only when the burst length is set to continuous.? removed from document.
90 s29cd016g s29cd016_00_a4 november 5, 2004 advance information revision a3 (may 26, 2004) block diagram on page 6 moved reset# to point to the state control/command register. figure 2, on page 22 updated note added ?double-word? to figure title. table 9, ?configuration register definitions,? on page 24 added ?cr14 = automatic sleep mode...? configurations. table 1, ?sector addresses for ordering option 00,? on page 33 re-inserted previously missing data. removed ?note 1? from sector sa1. added ?note 3? to sector sa44 and sa45. moved sectors sa15 - sa30 to bank 1. table on page 35 added ?note 3? to sector sa45. revision a4 (november 5, 2004) global added reference links added colophon updated trademark product selector guide removed note from product selector guide table block diagram changed text on input/output buffers to show dq0 to dq31 pin configuration changed text in acc description accelerated program and erase operations changed text in this paragraph table 5 change address text column. secsi sector entry command changed address text in this paragraph figure 18 changed time spec call out from 10 ns to t wadvh2 table 27 added new row for t wadvh2
november 5, 2004 s29cd016_00_a4 s29cd016g 91 advance information colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). please note that spansion llc will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance o f failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire pr otection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to cert ain restrictions on export under the foreign ex- change and foreign trade law of japan , the us export administration regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subject to change without notice. this document may contain information on a spansion llc pro duct under development by spansion llc. spansion llc reserves the right to change or discontinue work on any product without notice. the information in this document i s provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion llc assumes no liability for any damages of any kind arising out of the use of the information in this d ocument. copyright ?2004 spansion llc. all rights reserved. spansion, the spansion logo, and mirrorbit are trademarks of spansion llc. o ther company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

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